PAC7366

NTSC/PAL Digital Image SOC

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7

PixArt Imaging Inc.

V1.10

Dec. 2012

I

Fig.3.5 Definition of timing for F/S-mode devices on the I2C-bus.

I

Parameter

Symbol

Standard Mode

Unit

Min.

Max

SCL clock frequency.

10

400

KHz

Hold time ( repeated ) Start condition.

After this period, the first clock pulse is generated.

4.0

-

μs

Low period of the SCL clock.

4.7

-

μs

High period of the SCL clock.

0.75

-

μs

Set-up time for a repeated START condition.

4.7

-

μs

Data hold time. For I2C-bus device.

0

3.45

μs

Data set-up time.

250

-

ns

Rise time of both SDA and SCL signals.

30

N.D.

ns

( notel )

Fall time of both SDA and SCL signals.

30

N.D.

ns

( notel )

Set-up time for STOP condition.

4.0

-

μs

Bus free time between a STOP and START.

4.7

-

μs

Capacitive load for each bus line.

1

15

pF

Noise margin at LOW level for each connected device.

( Including hysteresis )

0.1

VDD

-

V

Noise margin at HIGH level for each connected device.

( including hysteresis )

0.2

VDD

-

V

Note: It depends on the “high” period time of SCL.