PAC7366 datasheet(6/23 Pages) PIXART

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PAC7366

NTSC/PAL Digital Image SOC

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PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.10

Dec. 2012

Data Transfer Format

Master transmits data to salve ( write cycle )

S : Start.

A : Acknowledge by salve.

P : Stop.

RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 –

Read cycle, RW = 0 – Write cycle.

SUBADDRESS : The address values of PAC7366 internal control registers. ( Please refer to

PAC7366 register description )

Fig.3.3 Master-transmitter transmits to slave-receiver

During write cycle, the master generates start condition and then places the 1st byte data that are

combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAC7366 )

issues acknowledgment, the master places 2nd and 3rd byte ( Sub Address ) data on SDA line. Again follow

the PAC7366 acknowledgment, the master places the 16 bits data on SDA line and transmit to PAC7366

control register ( address was assigned by 2nd and 3rd byte ). After PAC7366 issues acknowledgment, the

master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the

PAC7366 sub-address is automatically increment after each DATA byte transferred. The data and A cycles

is repeat until last byte write. Every control registers value inside PAC7366 can be programming via this

way.

Slave transmits data to master ( read cycle )

The sub-address was taken from previous write cycle.

The sub-address is automatically increment after each byte read.

Am : Acknowledge by master.

Note there is no acknowledgment from master after last byte read.

Fig.3.4 Slave-transmitter transmits to master-receiver

During read cycle, the master generates start condition and then place the 1st byte data that are combined

slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 16 bits

DATA was also placed on SDA line by PAC7366. The 16 bits data was read from PAC7366 internal

control register that address was assigned by previous write cycle. Follow the master acknowledgment,

the PAC7366 place the next 16 bits data ( address is increment automatically ) on SDA line and then

transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read,

Am is no longer generated by master but instead by keep SDA line high. The slave ( PAC7366 ) must

releases SDA line to master to generate STOP condition.

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