STM8L151C8 datasheet(111/134 Pages) STMICROELECTRONICS

номер детали	STM8L151C8

подробное описание детали	8-bit ultralow power MCU, up to 64 KB Flash 2 KB data EEPROM, RTC, LCD, timers, USARTs, I2C, SPIs, ADC, DAC, comparators

PDF	134 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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DocID17943 Rev 6

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STM8L15xx8, STM8L15xR6

Electrical parameters

121

9.3.13

12-bit DAC characteristics

In the following table, data are guaranteed by design, not tested in production.

Table 50. DAC characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

VDDA

Analog supply voltage

1.8

3.6

VREF+

Reference supply voltage

1.8

VDDA

IVREF

Current consumption on VREF+

supply

VREF+ = 3.3 V, no load,

middle code (0x800)

130

220

µA

VREF+ = 3.3 V, no load,

worst code (0x000)

220

350

IVDDA

Current consumption on VDDA

supply

VDDA = 3.3 V, no load,

middle code (0x800)

210

320

VDDA = 3.3 V, no load,

worst code (0x000)

320

520

Temperature range

-40

125

°C

RL(1) (2)

Resistive load

DACOUT buffer ON

Output impedance

DACOUT buffer OFF

CL(3)

Capacitive load

DAC_OUT

(4)

DAC_OUT voltage

DACOUT buffer ON

0.2

VDDA - 0.2

DACOUT buffer OFF

VREF+ -1 LSB

tsettling

Settling time (full scale: for a 12-

bit input code transition between

the lowest and the highest input

codes when DAC_OUT reaches

the final value ±1LSB

)

RL ≥ 5 kΩ, CL≤ 50 pF

712

µs

Update rate

Max frequency for a correct

DAC_OUT (@95%) change

when small variation of the input

code (from code i to i+1LSB).

RL ≥ 5kΩ, CL ≤50 pF

Msps

tWAKEUP

Wakeup time from OFF state.

Input code between lowest and

highest possible codes.

RL ≥ 5kΩ, CL≤50 pF

915

µs

PSRR+

Power supply rejection ratio (to

VDDA) (static DC measurement)

RL≥ 5kΩ, CL≤50 pF

-60

-35

1. Resistive load between DACOUT and GNDA

2. Output on PF0 or PF1

3. Capacitive load at DACOUT pin

4. It gives the output excursion of the DAC

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