A43L8316 datasheet(13/45 Pages) AMICC

13 / 45 page

A43L8316

Preliminary (April, 2000, Version 1.0)

AMIC Technology, Inc.

Device Operations

Clock (CLK)

The clock input is used as the reference for all SDRAM

operations. All operations are synchronized to the positive

going edge of the clock. The clock transitions must be

monotonic between VIL and VIH. During operation with

CKE high all inputs are assumed to be in valid state (low or

high) for the duration of set up and hold time around

positive edge of the clock for proper functionality and ICC

specifications.

Clock Enable (CLK)

The clock enable (CKE) gates the clock onto SDRAM. If

CKE goes low synchronously with clock (set-up and hold

time same as other inputs), the internal clock is suspended

form the next clock cycle and the state of output and burst

address is frozen as long as the CKE remains low. All

other inputs are ignored from the next clock cycle after

CKE goes low. When both banks are in the idle state and

CKE goes low synchronously with clock, the SDRAM

enters the power down mode form the next clock cycle.

The SDRAM remains in the power down mode ignoring the

other inputs as long as CKE remains low. The power down

exit is synchronous as the internal clock is suspended.

When CKE goes high at least “tSS + 1 CLOCK” before the

high going edge of the clock, then the SDRAM becomes

active from the same clock edge accepting all the input

commands.

Bank Select (BA)

This SDRAM is organized as two independent banks of

131,072 words X 16 bits memory arrays. The BA inputs is

latched at the time of assertion of RAS and CAS to select

the bank to be used for the operation. When BA is asserted

low, bank A is selected. When BA is asserted high, bank B

is selected. The bank select BA is latched at bank activate,

read, write mode register set and precharge operations.

Address Input (A0 ~ A8/AP)

The 17 address bits required to decode the 131,072 word

locations are multiplexed into 9 address input pins

(A0~A8/AP). The 11 bit row address is latched along with

RAS and BA during bank activate command. The 8 bit

column address is latched along with CAS , WE and BA

during read or write command.

NOP and Device Deselect

When RAS , CAS

and

WE are high, the SDRAM

performs no operation (NOP). NOP does not initiate any

new operation, but is needed to complete operations which

require more than single clock like bank activate, burst

read, auto refresh, etc. The device deselect is also a NOP

and is entered by asserting CS high. CS

high disables

the command decoder so that RAS , CAS and WE , and

all the address inputs are ignored.

Power-Up

The following sequence is recommended for POWER UP

1. Power must be applied to either CKE and DQM inputs to

pull them high and other pins are NOP condition at the

inputs before or along with VDD (and VDDQ) supply.

The clock signal must also be asserted at the same time.

2. After VDD reaches the desired voltage, a minimum

pause of 200 microseconds is required with inputs in

NOP condition.

3. Both banks must be precharged now.

4. Perform a minimum of 2 Auto refresh cycles to stabilize

the internal circuitry.

5. Perform a MODE REGISTER SET cycle to program the

CAS latency, burst length and burst type as the default

value of mode register is undefined.

At the end of one clock cycle from the mode register set

cycle, the device is ready for operation.

When the above sequence is used for Power-up, all the

out-puts will be in high impedance state. The high

impedance of outputs is not guaranteed in any other

power-up sequence.

cf.) Sequence of 4 & 5 may be changed.

Mode Register Set (MRS)

The mode register stores the data for controlling the

various operation modes of SDRAM. It programs the CAS

latency, addressing mode, burst length, test mode and

various vendor specific options to make SDRAM useful for

variety of different applications. The default value of the

mode register is not defined, therefore the mode register

must be written after power up to operate the SDRAM. The

mode register is written by asserting low on CS ,RAS ,

CAS , WE (The SDRAM should be in active mode with

CKE already high prior to writing the mode register). The

state of address pins A0~A8/AP and BA in the same cycle

as CS ,RAS , CAS , WE going low is the data written in

the mode register. One clock cycle is required to complete

the write in the mode register. The mode register contents

can be changed using the same command and clock cycle

requirements during operation as long as both banks are in

the idle state. The mode register is divided into various

fields depending on functionality. The burst length field

uses A0~A2, burst type uses A3, addressing mode uses

A4~A6, A7~A8/AP and BA are used for vendor specific

options or test mode. And the write burst length is

programmed using BA. A7~A8/AP and BA must be set to

low for normal SDRAM operation.

Refer to table for specific codes for various burst length,

addressing modes and CAS latencies.

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