LTC4267CDHC datasheet(24/32 Pages) LINEAR

24 / 32 page

LTC4267

4267fc

Selecting the Switching Transistor

With the N-channel power MOSFET driving the primary of

the transformer, the inductance will cause the drain of the

MOSFET to traverse twice the voltage across VPORTP and

PGND. The LTC4267 operates with a maximum supply of

– 57V; thus the MOSFET must be rated to handle 114V or

more with sufﬁcient design margin. Typical transistors have

150V ratings while some manufacturers have developed

120V rated MOSFETs speciﬁcally for Power-over-Ethernet

applications.

The NGATE pin of the LTC4267 drives the gate of the

N-channel MOSFET. NGATE will traverse a rail-to-rail volt-

age from PGND to PVCC. The designer must ensure the

MOSFET provides a low “ON” resistance when switched

to PVCC as well as ensure the gate of the MOSFET can

handle the PVCC supply voltage.

For high efﬁciency applications, select an N-channel

MOSFET with low total gate charge. The lower total gate

charge improves the efﬁciency of the NGATE drive circuit

and minimizes the switching current needed to charge

and discharge the gate.

Auxiliary Power Source

In some applications, it may be desirable to power the

PD from an auxiliary power source such as a wall trans-

former. The auxiliary power can be injected into the PD at

several locations and various trade-offs exist. Power can

be injected at the 3.3V or 5V output of the isolated power

supply with the use of a diode ORing circuit. This method

accesses the internal circuits of the PD after the isolation

barrier and therefore meets the 802.3af isolation safety

requirements for the wall transformer jack on the PD.

Power can also be injected into the PD interface portion

of the LTC4267. In this case, it is necessary to ensure the

user cannot access the terminals of the wall transformer

jack on the PD since this would compromise the 802.3af

isolation safety requirements.

Figure 16 demonstrates three methods of diode ORing

external power into a PD. Option 1 inserts power before

the LTC4267 interface controller while options 2 and 3

bypass the LTC4267 interface controller section and power

the switching regulator directly.

If power is inserted before the LTC4267 interface con-

troller, it is necessary for the wall transformer to exceed

the LTC4267 UVLO turn-on requirement and include a

transient voltage suppressor (TVS) to limit the maximum

voltage to 57V. This option provides input current limit

for the transformer, provides a valid power good signal,

and simpliﬁes power priority issues. As long as the wall

transformer applies power to the PD before the PSE, it

will take priority and the PSE will not power up the PD

because the wall power will corrupt the 25kΩ signature. If

the PSE is already powering the PD, the wall transformer

power will be in parallel with the PSE. In this case, prior-

ity will be given to the higher supply voltage. If the wall

transformer voltage is higher, the PSE should remove the

line voltage since no current will be drawn from the PSE.

On the other hand, if the wall transformer voltage is lower,

the PSE will continue to supply power to the PD and the

wall transformer will not be used. Proper operation should

occur in either scenario.

If auxiliary power is applied directly to the LTC4267 switch-

ing regulator (bypassing the LTC4267 PD interface), a

different set of tradeoffs arise. In the conﬁguration shown

in option 2, the wall transformer does not need to exceed

the LTC4267 turn-on UVLO requirement; however, it is

necessary to include diode D9 to prevent the transformer

from applying power to the LTC4267 interface controller.

The transformer voltage requirement will be governed by

the needs of the onboard switching regulator. However,

power priority issues require more intervention. If the

wall transformer voltage is below the PSE voltage, then

priority will be given to the PSE power. The LTC4267

interface controller will draw power from the PSE while

the transformer will sit unused. This conﬁguration is not

a problem in a PoE system. On the other hand, if the wall

APPLICATIO S I FOR ATIO

Figure 15. Main Loop Compensation for a Nonisolated Design

LTC4267

ITH/RUN

PGND

4267 F15

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