AM79C982 datasheet(20/26 Pages) AMD

20 / 26 page

AMD

PRELIMINARY

1–22

Am79C982

B Bit Rate Error. This bit is set to 1 if there has been an

instance of FIFO Overflow or Underflow, caused by

data received at the AUI port. This bit is cleared when

the status is read.

S SQE Test Status. This bit is set to 1 if SQE Test is

detected by the bIMR chip. This bit is cleared when

the status is read. A MAU attached to a repeater

must have SQE Test disabled. This bit is set even if

the AUI port is disabled or partitioned.

L Loop Back Error. The MAU attached to the AUI is

required to loopback data transmitted to DO onto the

DI circuit. If loopback carrier is not detected by the

bIMR device, then this bit is set to 1 to report this

condition. This bit is cleared when the status is read.

For a repeater this is the only indication of a broken

or missing MAU.

TP Port Partitioning Status

SI data:

10000000

SO data:

P7....................P0 (bIMR8)

SO data:

P3 X P2 X P1 X P0 (bIMR4)

X = don’t care

Pn = 0

TP port n partitioned

Pn = 1

TP port n connected

The partitioning Status of all four or eight TP ports are

accessed by this command. If a port is disabled, reading

it partitioning status will indicate that it is connected.

Bit Rate Error Status of TP Ports

SI data:

10100000

SO data:

E7....................E0 (bIMR8)

SO data:

E3 X E2 X E1 X E0 (bIMR4)

X = don’t care

This allows a single command to be used to report Bit

Rate Error condition (FIFO Overflow or Underflow) of all

Twisted Pair ports. The 8 bits (4 bits) of the output pat-

tern correspond to each of the 8 TP (4 TP) ports, with

least significant bit corresponding to port 0.

The status bit for a port is set to 1 if there has been an

instance when data received from that port has caused

a FIFO error.

All status bits stay set until the status is read.

Link Test Status of TP Ports

SI data:

11010000

SO data:

L7....................L0 (bIMR8)

SO data:

L3 X L2 X L1 X L0 (bIMR4)

X = don’t care

Ln = 0

TP Port n in Link Test Fail

Ln = 1

TP Port n in Link Test Pass

The Link Test Status of all eight (four) TP ports are ac-

cessed by this command. A disabled port continues to

report correct Link Test Status. Re-enabling a disabled

port causes the port to be placed into Link Test Fail

state. This ensures that packet fragments received on

the port are not repeated to the rest of the network.

Receive Polarity Status of TP Ports

SI data:

11100000

SO data:

P7....................P0 (bIMR8)

SO data:

P3 X P2 X P1 X P0 (bIMR4)

X = don’t care

Pn = 0

TP Port n Polarity Correct

Pn = 1

TP Port n Polarity Reversed

The statuses of all eight (four) TP port polarities are ac-

cessed with this command. The bIMR chip has the abil-

ity to detect and correct reversed polarity on the TP

ports’ RXD+/– pins. If the polarity is detected as re-

versed for a TP port, then the bIMR chip will set the ap-

propriate bit in this command’s result byte only if the

Polarity Reversal Function is enabled for that port.

MJLP Status

SI data:

11110000

SO data:

M00000000

Each bIMR chip contains an independent MAU Jabber

Lock Up Protection Timer. The timer is designed to in-

hibit the bIMR device transmit function, if it has been

transmitting continuously for more than 65536 Bit

Times. The MJLP Status bit (M) is set to 1 if this hap-

pens. This bit remains set and is only cleared when the

MJLP status is read by using this command.

Version

SI data:

11111111

SO data:

XXXX0001

This command (1111 1111) can be used to determine

the device version.

The bIMR chip responds by the bit pattern: XXXX 0101

AM79C982 датащи(PDF) 20 Page - Advanced Micro Devices

AM79C982 датащи(HTML) 20 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

датащи скачать

ссылки URL