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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C976 датащи(PDF) 144 Page - Advanced Micro Devices |
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AM79C976 датащи(HTML) 144 Page - Advanced Micro Devices |
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144 / 309 page  144 Am79C976 8/01/00 P R E L I M INARY &75/ &RQWURO 5HJLVWHU Offset 074h All bits in this register are set to their default values by H_RESET. All bits are also set to their default values before EEPROM data are loaded or after an EEPROM read failure. The default value for all bits is 0. Table 49. CTRL3: Control3 Register Table 50. Software Styles 3 XPHYSP External PHY Speed. When set, this bit will force the external PHY into 100 Mbps mode when Auto- Negotiation is not enabled. XPHYSP is only valid when the internal Network Port Manager is scanning for a network port. This bit is an alias of BCR32, bit 3. 2-0 APDW MII Auto-Poll Dwell Time. APDW determines the dwell time between MII Management Frames accesses when Auto-Poll is turned on. The default value of this field is 100b. This field is an alias of BCR32, bits 10:8. Bit Name Description APDW Auto-Poll É Dwell Time 000 Continuous (26 ms @ 2.5 MHz) 001 Every 64 MDC cycles (51 ms @ 2.5 MHz) 010 Every 128 MDC cycles (103 ms @ 2.5 MHz) 011 Every 256 MDC cycles (206 ms @ 2.5 MHz) 100 Every 512 MDC cycles (410 ms @ 2.5 MHz) 101 Every 1024 MDC cycles (819 ms @ 2.5 MHz) 110-111 Reserved Bit Name Description 31-8 RES Reserved locations. Written as zeros and read as undefined. 7-0 SWSTYLE Software Style register. The value in this register determines the style of register and memory resources that shall be used by the Am79C976 controller. The Software Style selection will affect the interpretation of a few bits within the CSR space, the order of the descriptor entries, and the width of the descriptors and initialization block entries. All Am79C976 controller CSR bits and BCR bits and all descriptor, buffer, and initialization block entries not cited in Table 50 are unaffected by the Software Style selection and are, therefore, always fully functional as specified in the CSR and BCR sections. SWSTYLE [7:0] Style Name SSIZE32 Initialization Block Entries Descriptor Ring Entries 00h LANCE/ PCnet-ISA controller 0 16-bit software structures, non-burst or burst access 16-bit software structures, non- burst access only 01h RES 1 RES RES |
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