AM79C976 datasheet(143/309 Pages) AMD

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8/01/00

Am79C976

143

P R E L I M INARY

CTRL2: Control2 Register

Offset 070h

This register contains several miscellaneous control

bits. Each byte of this register controls a single func-

tion. It is not necessary to do a read-modify-write oper-

ation to change a function’s settings if only a single byte

of the register is written.

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits except for bits 2:0 (APDW)

is 0. The default value for the APDW field is 100b.

Table 48. CTRL2: Control2 Register

Bit

Name

Description

31-19

RES

Reserved locations. Written as zeros and read as undefined.

18-16

Force Speed. This three-bit field sets the MAC’s internal speed indicator according to the table

below. The speed indication is used only for LEDs.

15-10

RES

Reserved locations. Written as zeros and read as undefined.

9-8

FMDC

Fast Management Data Clock. When FMDC is set to 2h the MII Management Data Clock will run

at 10 MHz max. The Management Data Clock will no longer be IEEE 802.3u-compliant and setting

this bit should be used with care. The accompanying external PHY must also be able to accept

management frames at the new clock rate. When FMDC is set to 1h, the MII Management Data

Clock will run at 5 MHz max. The Management Data Clock will no longer be IEEE 802.3u-compliant

and setting this bit should be used with care. The accompanying external PHY must also be able

to accept management frames at the new clock rate. When FMDC is set to 0h, the MII Management

Data Clock will run at 2.5 MHz max and will be fully compliant to IEEE 802.3u standards.

This field is an alias of BCR32, bits13:12

RES

Reserved location. Written as zero and read as undefined.

XPHYRST

External PHY Reset. When XPHYRST is set, the Am79C976 controller after an H_RESET or

S_RESET will issue an MII management frame that will reset the external PHY. This bit is needed

when there is no way to guarantee the state of the external PHY. This bit must be reprogrammed

after every H_RESET.

XPHYRST is only valid when the internal Network Port Manager is scanning for a network port.

This bit is an alias of BCR32, bit 6.

5XPHYANE

External PHY Auto-Negotiation Enable. This bit will force the external PHY into enabling Auto-

Negotiation. When set to 0 the Am79C976 controller will send an MII management frame disabling

Auto-Negotiation.

XPHYANE is only valid when the internal Network Port Manager is scanning for a network port.

This bit is an alias of BCR32, bit 5.

XPHYFD

External PHY Full Duplex. When set, this bit will force the external PHY into full duplex when Auto-

Negotiation is not enabled.

XPHYFD is only valid when the internal Network Port Manager is scanning for a network port.

This bit is an alias of BCR32, bit 4.

FS[2:0]

Speed

000

Speed determined by PHY

001

Reserved

010

10 Mb/s

011

100 Mb/s

1XX

Reserved

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