AM79C976 datasheet(130/309 Pages) AMD

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Am79C976

8/01/00

P R E L I M INARY

&0' &RPPDQG

Offset 048h

CMD0 is a command-style register. All bits in this reg-

ister are cleared to 0 when the RST pin is asserted, be-

fore the serial EEPROM is read, and after a serial

EEPROM read error.

Table 42. CMD0: Command0 Register

Bit

Name

Description

31-16

RES

Reserved locations. Written as zeros and read as undefined.

VAL1

Value bit for byte 1. The value of this bit is written to any bits in the CMD0 register that correspond

to bits in the CMD0[14:8] bit map field that are set to 1.

14-13

RES

Reserved locations. Written as zeros and read as undefined.

RDMD

Receive Demand, when set, causes the Descriptor Management Unit to access the Receive

Descriptor Ring without waiting for the chain poll-time counter to expire.

11-9

RES

Reserved locations. Written as zeros and read as undefined.

8TDMD

Transmit Demand, when set, causes the Buffer Management Unit to access the Transmit

Descriptor Ring without waiting for the poll-time counter to elapse. If TXON is not enabled, TDMD

bit will be reset and no Transmit Descriptor Ring access will occur.

If the TXDPOLL bit in CMD2 is set, the host processor must set TDMD each time it is ready for the

Am79C976 device to poll the Transmit Descriptor Ring. When TXDPOLL = 0, setting TDMD merely

hastens the Am79C976 controller’s next access to a Transmit Descriptor Ring Entry.

7VAL0

Value bit for byte 0. The value of this bit is written to any bits in the CMD0 register that correspond

to bits in the CMD0[6:0] bit map field that are set to 1.

6UINTCMD

User Interrupt Command. UINTCMD can be used by the host to generate an interrupt unrelated to

any network activity. Writing a 1 to this bit causes the UINT bit in the Interrupt Register to be set to

1, which in turn causes INTA to be asserted if interrupts are enabled.

UINTCMD is always read as 0.

RX_FAST_

SPND

Receive Fast Suspend. Setting this bit causes the receiver to suspend its activities as quickly as

possible without stopping in the middle of a frame reception. Setting RX_FAST_SPND does not

stop the DMA controller from transferring frame data from the receive FIFO to host memory.

If a frame is being received at the time that RX_FAST_SPND is set to 1, the reception of that frame

will be completed, but no more frames will be received until RX_FAST_SPND is cleared to 0.

After the receiver has suspended its activity, the RX_SUSPENDED bit in the Status register and

the Suspend Interrupt (SPNDINT) bit in the Interrupt register will be set, which will cause an

interrupt to occur if interrupts are enabled and the SPNDINTEN bit in the Interrupt Enable register

is set.

TX_FAST_SPND

Transmit Fast Suspend. Setting this bit causes the transmitter to suspend its activities as quickly

as possible without stopping in the middle of a frame transmission. Setting TX_FAST_SPND does

not stop the DMA controller from transferring frame data from host memory to the transmit FIFO.

If a frame is being transmitted at the time that TX_FAST_SPND is set to 1, the transmission of that

frame will be completed, but no more frames will be transmitted until TX_FAST_SPND is cleared

to 0.

After the transmitter has suspended its activity, the TX_SUSPENDED bit in the Status register and

the Suspend Interrupt (SPNDINT) bit in the INT0 register will be set, which will cause an interrupt

to occur if interrupts are enabled and the SPNDINTEN bit in the Interrupt Enable register is set.

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