AM79C976 datasheet(119/309 Pages) AMD

119 / 309 page

8/01/00

Am79C976

119

P R E L I M INARY

ister, which can be loaded from the serial EEPROM. It

is recommended that the shadow register be pro-

grammed to a value of 18h, which corresponds to 6 µs.

The host should use the value in this register to deter-

mine the setting of the PCI Latency Timer register.

The PCI MIN_GNT register is read only.

3&, 0$;B/$7 5HJLVWHU

Offset 3Fh

The PCI MAX_LAT register is an 8-bit register that spec-

ifies the maximum arbitration latency the Am79C976

controller can sustain without causing problems to the

network activity. The register value specifies the time in

units of 1/4 µs. The MAX_LAT register is an alias of the

Maximum Latency Shadow Register, which can be load-

ed from the serial EEPROM. It is recommended that the

shadow register be programmed to a value of 18h,

which corresponds to 6 µs.

The host should use the value in this register to deter-

mine the setting of the PCI Latency Timer register.

The PCI MAX_LAT register is read only

3&, &DSDELOLW\ ,GHQWLILHU 5HJLVWHU

Offset 44h

Bit

Name

Description

7-0

CAP_ID

This register identifies the linked

list item as being the PCI Power

Management registers. This is a

read-only register whose value is

fixed at 1h.

3&, 1H[W ,WHP 3RLQWHU 5HJLVWHU

Offset 45h

Bit

Name

Description

7-0

NXT_ITM_PTR

The Next Item Pointer Register

points to the starting address of

the next capability. The pointer at

this offset is a null pointer, indi-

cating that this is the last capabil-

ity in the linked list of the

capabilities. This is a read-only

3&, 3RZHU 0DQDJHPHQW&DSDELOLWLHV5HJLVWHU

30&

Offset 46h

Note: All bits of this register are loaded from

EEPROM. The register is aliased to BCR36 for testing

purposes.

Bit

Name

Description

15-11

PME_SPT

PME Support. This 5-bit field indi-

cates the power states in which

the function may assert PME. A

value of 0b for any bit indicates

that the function is not capable of

asserting the PME signal while in

that power state.

Bit(11) XXXX1b - PME can be

asserted from D0.

Bit(12) XXX1Xb - PME can be

asserted from D1.

Bit(13) XX1XXb - PME can be

asserted from D2.

Bit(14) X1XXXb - PME can be

asserted from D3hot.

Bit(15) 1XXXXb - PME can be

asserted from D3cold. The value

read from bit(15) is the AND of

the value of BCR36, bit 15 and

the

current

state

the

VAUX_SENSE pin.

Read only.

D2_SPT

D2 Support. If this bit is a 1, this

function supports the D2 Power

Management State.

Read only.

D1_SPT

D1 Support. If this bit is a 1, this

function supports the D1 Power

Management State.

Read only.

8-6

RES

Reserved locations. Written and

read as zeros.

DSI

Device

Specific

Initialization.

When this bit is 1, it indicates that

special initialization of the func-

tion is required (beyond the stan-

dard PCI configuration header)

before the generic class device

driver is able to use it.

Read only.

RES

Reserved location. Written and

read as zero.

AM79C976 датащи(PDF) 119 Page - Advanced Micro Devices

AM79C976 датащи(HTML) 119 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL