AM79C976 datasheet(117/309 Pages) AMD

117 / 309 page

8/01/00

Am79C976

117

P R E L I M INARY

ID is an alias of BCR23, bits 15-0. It is programmable

through the EEPROM.

The PCI Subsystem Vendor ID register is read only.

3&, 6XEV\VWHP,' 5HJLVWHU

Offset 2Eh

The PCI Subsystem ID register is a 16-bit register that

together with the PCI Subsystem Vendor ID uniquely

identifies the add-in card or subsystem the Am79C976

controller is used in. The value of the Subsystem ID is

up to the system vendor. A value of 0 (the default) indi-

cates that the Am79C976 controller does not support

subsystem identification. The PCI Subsystem ID is an

alias of BCR24, bits 15-0. It is programmable through

the EEPROM.

The PCI Subsystem ID register is read only.

3&, ([SDQVLRQ520 %DVH$GGUHVV 5HJLVWHU

Offset 30h

The PCI Expansion ROM Base Address register is a

32-bit register that defines the base address, size and

address alignment of an Expansion ROM. The host

CPU can determine the size and alignment require-

ments of the ROM by writing all 1s to this register, read-

ing back the result, and masking out the least

significant bit. The device will return 0s in all don’t care

bits.

The Am79C976 device supports ROMs ranging in size

from 2 kbytes to 16 Mbytes. The amount of address

space claimed by the ROM can be programmed

through the ROM Configuration register, which can be

loaded from the external serial EEPROM. The bits of

the ROM Configuration Register (ROM_CFG) act as

write enable bits for bits [23:11] and bit 0 of this register.

See Figure 4646.

As an example, assume that ROM_CFG is pro-

grammed to 0F001h. This means that bits [23:20] and

bit 0 of ROMBASE are write enabled, and bits [19:11]

are fixed at 0. In addition, bits [31:24] of ROMBASE are

always write enabled, and bits [10:1] are always 0, re-

gardless of the contents of ROM_CFG. Therefore,

when the host CPU writes all 1s to ROMBASE, it will

read back 0FFF00001h. Masking out bit 0 leaves

0FFF00000h. This means that bits [19:0] of the base

address are don’t cares, and the ROM occupies 220 or

1 Mbytes of address space, and must be mapped to a

1 Mbyte boundary. If the CPU then writes 00300001h

to this register and sets the MEMEN bit (PCI Command

will claim the memory space between 00300000h and

003FFFFFh.

)LJXUH 3&, ([SDQVLRQ520 %DVH $GGUHVV 5HJLVWHU

Note: The procedure described in the PCI Expansion

ROM Base Address Register section specifies the

amount of address space that the ROM claims. The

ROM may be smaller than the amount of address

space claimed. The actual size of the code in the Ex-

pansion ROM is always determined by reading the Ex-

pansion ROM header.

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