AM79C976 datasheet(118/309 Pages) AMD

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118

Am79C976

8/01/00

P R E L I M INARY

Bit

Name

Description

31-24

ROMBASE Expansion ROM base address

most significant 8 bits. These bits

are written by the host to specify

the location of the Expansion

ROM in PCI memory space.

ROMBASE must be written with a

valid

address

before

the

Am79C976 Expansion ROM ac-

cess

enabled

setting

ROMEN (PCI Expansion ROM

Base Address register, bit 0) and

MEMEN (PCI Command register,

bit 1).

When the Am79C976 controller

is enabled for Expansion ROM

access (ROMEN and MEMEN

are set to 1), it monitors the PCI

bus for a valid memory com-

mand. If the value on AD[31:2]

during the address phase of the

cycle falls in the address space

specified by the contents of this

ler will drive DEVSEL indicating it

will respond to the access.

ROMBASE is read and written by

the host. ROMBASE is cleared

by H_RESET and is not affected

by S_RESET or by setting the

STOP bit.

23-11

ROMSIZE

Expansion ROM base address

bits [23:11]. Those bits in this

field that are enabled by the cor-

responding bits in the ROM Con-

figuration Register (ROM_CFG)

are written by the host CPU to

specify the location of the Expan-

sion ROM in PCI memory space.

Those bits in this field that are not

enabled by the corresponding

bits in ROM_CFG are fixed at 0.

10-1

ZEROS

Read as zeros; write operation

has no effect.

ROMEN

Expansion ROM Enable. Written

by the host to enable access to

the

Expansion

ROM.

The

Am79C976 controller will only re-

spond to accesses to the Expan-

sion ROM when both ROMEN

and MEMEN (PCI Command reg-

ister, bit 1) are set to 1. This bit

can be set to 1 only when bit 0 of

ROM_CFG is set to 1. When bit 0

of ROM_CFG is cleared to 0,

ROMEN is fixed a 0, and the Ex-

pansion ROM cannot be mapped

into PCI memory space.

ROMEN is read and written by

the host. ROMEN is cleared by

H_RESET and is not effected by

S_RESET or by setting the STOP

bit.

3&,&DSDELOLWLHV 3RLQWHU 5HJLVWHU

Offset 34h

Bit

Name

Description

7-0

CAP_PTR

The

PCI

Capabilities

pointer

ister that points to a linked list of

capabilities implemented on this

device. This register has the val-

ue 44h.

The PCI Capabilities register is

read only.

3&,,QWHUUXSW /LQH 5HJLVWHU

Offset 3Ch

The PCI Interrupt Line register is an 8-bit register that

is used to communicate the routing of the interrupt.

This register is written by the POST software as it ini-

tializes the Am79C976 controller in the system. The

interrupt channel which the POST software has as-

signed to the Am79C976 controller. The PCI Interrupt

Line register is not modified by the Am79C976 control-

ler. It has no effect on the operation of the device.

The PCI Interrupt Line register is read and written by

the host. It is cleared by H_RESET and is not affected

by S_RESET or by setting the STOP bit.

3&,,QWHUUXSW 3LQ5HJLVWHU

Offset 3Dh

This PCI Interrupt Pin register is an 8-bit register that

indicates the interrupt pin that the Am79C976 controller

is using. The value for the Am79C976 Interrupt Pin reg-

ister is 01h, which corresponds to INTA.

The PCI Interrupt Pin register is read only.

3&,0,1B*17 5HJLVWHU

Offset 3Eh

The PCI MIN_GNT register is an 8-bit register that

specifies the minimum length of a burst period that the

Am79C976 device needs to keep up with the network

activity. The length of the burst period is calculated as-

suming a clock rate of 33 MHz. The register value spec-

ifies the time in units of 1/4 µs. The PCI MIN_GNT

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