AM79C976 datasheet(195/309 Pages) AMD

195 / 309 page

8/01/00

Am79C976

195

P R E L I M INARY

by S_RESET or setting the STOP

bit.

RWU_DRIVER RWU Driver Type. If this bit is set

to 1, RWU is a totem pole driver;

otherwise RWU is an open drain

output.

Read/Write accessible. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

RWU_GATE RWU Gate Control. If this bit is

set, RWU is forced to the high Im-

pedance State when PG is LOW,

regardless of the state of the

MPMAT and LCDET bits.

Read/Write accessible. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

RWU_POL RWU Pin Polarity. If RWU_POL

is set to 1, the RWU pin is normal-

ly HIGH and asserts LOW; other-

wise, RWU is normally LOW and

asserts HIGH.

Read/Write accessible. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

RST_POL

PHY_RST Pin Polarity. If the

PHY_POL

set

the

PHY_RST pin is active LOW; oth-

erwise,

PHY_RST

active

HIGH.

Read/Write accessible. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

&65 5HVHUYHG

Bit

Name

Description

31-0

RES

Reserved locations. Written as

zeros and read as undefined.

&65 $GYDQFHG )HDWXUH &RQWURO

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-2

RES

Reserved locations. Written as

zeros and read as undefined.

RCVALGN

Receive Packet Align. When set,

this bit forces the data field of ISO

8802-3 (IEEE/ANSI 802.3) pack-

ets to align to 0 MOD 4 address

boundaries (i.e., DWord aligned

addresses). It is important to note

that this feature will only function

correctly if all receive buffer

boundaries are DWord aligned

and all receive buffers have 0

MOD 4 lengths. In order to ac-

complish the data alignment, the

Am79C976 controller simply in-

serts two bytes of random data at

the beginning of the receive

packet (i.e., before the ISO 8802-

3 (IEEE/ANSI 802.3) destination

address field). The MCNT field

reported to the receive descriptor

will not include the extra two

bytes.

Read/Write

accessible.

RCVALGN

cleared

H_RESET or S_RESET and is

not affected by STOP.

&65 5HVHUYHG

Bit

Name

Description

31-0

RES

Reserved locations. Written as

zeros and read as undefined.

&65 7HVW5HJLVWHU

This register is used to place the Am79C976 controller

into various test modes. The Runt Packet Accept is the

only user accessible test mode. All other test modes are

for AMD internal use only.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-4

RES

Reserved locations. Written as

zeros and read as undefined.

RPA

Runt Packet Accept. This bit forc-

es the Am79C976 controller to

accept runt packets (packets

shorter than 64 bytes).

The minimum packet size that

can be received is 12 bytes.

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