AM79C976 datasheet(196/309 Pages) AMD

196 / 309 page

196

Am79C976

8/01/00

P R E L I M INARY

Read/Write accessible. RPA is

cleared

H_RESET

S_RESET and is not affected by

STOP.

2-0

RES

Reserved locations. Written as

zeros and read as undefined.

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Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-8

IPG

Inter Packet Gap. This value indi-

cates the minimum number of

network bit times after the end of

a frame that the transmitter will

wait before it starts transmitting

another frame.

In half-duplex

mode the end of the frame is de-

termined by CRS, while in full-du-

plex mode the end of the frame is

determined by TX_EN. The IPG

value can be adjusted to com-

pensate for delays through the

external PHY device.

IPG should be programmed to

the nearest nibble. The two least

significant bits are ignored. For

example, programming IPG to

63h has the same effect as pro-

gramming it to 60h.

CAUTION: Use this parameter

with care. By lowering the IPG

below the IEEE 802.3 standard

96 bit times, the Am79C976 con-

troller can interrupt normal net-

work behavior.

Read/Write accessible. IPG is set

60h

(96

Bit

times)

H_RESET or S_RESET and is

not affected by STOP.

7-0

IFS1

InterFrameSpacingPart1.

Changing IFS1 allows the user to

program the value of the Inter-

Frame-SpacePart1 timing. The

Am79C976 controller sets the de-

fault value at 60 bit times (3ch).

See the subsection on Medium

Allocation in the section Media

Access Management for more

details. The equation for setting

IFS1 when IPG

96 bit times is:

IFS1 = IPG - 36 bit times

IPG should be programmed to

the nearest nibble. The two least

significant bits are ignored. For

example, programming IPG to

63h has the same effect as pro-

gramming it to 60h.

Read/Write accessible. IFS1 is

set to 3ch (60 bit times) by

H_RESET or S_RESET and is

not affected by STOP.

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