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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C976 датащи(PDF) 191 Page - Advanced Micro Devices |
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AM79C976 датащи(HTML) 191 Page - Advanced Micro Devices |
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191 / 309 page  8/01/00 Am79C976 191 P R E L I M INARY &65 5HVHUYHG Bit Name Description 31-0 RES Reserved locations. Written as zeros and read as undefined. &65 5HFHLYH5LQJ/HQJWK Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 RCVRL Receive Ring Length. Contains the two’s complement of the re- ceive descriptor ring length. This register is initialized during the optional Am79C976 controller ini- tialization routine based on the value in the RLEN field of the ini- tialization block. However, this register can be manually altered. The actual receive ring length is defined by the current value in this register. The ring length can be defined as any value from 1 to 65535. Read/Write accessible. These bits are unaffected by H_RESET, S_RESET, or STOP. &65 5HVHUYHG Bit Name Description 31-0 RES Reserved locations. Written as zeros and read as undefined. &65 7UDQVPLW 5LQJ /HQJWK Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 XMTRL Transmit Ring Length. Contains the two’s complement of the transmit descriptor ring length. This register is initialized during the optional Am79C976 control- ler initialization routine based on the value in the TLEN field of the initialization block. However, this register can be manually altered. The actual transmit ring length is defined by the current value in this register. The ring length can be defined as any value from 1 to 65535. Read/Write accessible. These bits are unaffected by H_RESET, S_RESET, or STOP. &65 5HVHUYHG Bit Name Description 31-0 RES Reserved locations. Written as zeros and read as undefined. &65 '0$ 7UDQVIHU &RXQWHU DQG ),)2 7KUHVKROG &RQWURO Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-14 RES Reserved locations. Written as zeros and read as undefined. 13-12 RCVFW[1:0]Receive FIFO Watermark. RCVFW controls the point at which receive DMA is requested in relation to the number of re- ceived bytes in the Receive FIFO. RCVFW specifies the num- ber of bytes which must be present (once the frame has been verified as a non-runt) be- fore receive DMA is requested. Note however that, if the network interface is operating in half-du- plex mode, in order for receive DMA to be performed for a new frame, at least 64 bytes must have been received. This effec- tively avoids having to react to re- ceive frames which are runts or suffer a collision during the slot time (512 bit times). If the Runt Packet Accept feature is enabled or if the network interface is oper- ating in full-duplex mode, receive DMA will be requested as soon as either the RCVFW threshold is reached, or a complete valid re- ceive frame is detected (regard- less of length). When the Full Duplex Runt Packet Accept Dis- able (FDRPAD) bit (BCR9, bit 2) is set and the Am79C976 control- ler is in full-duplex mode, in order for receive DMA to be performed for a new frame, at least 64 bytes must have been received. This effectively disables the runt pack- et accept feature in full duplex. |
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