AM79C970A datasheet(181/219 Pages) AMD

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P R E L I M I N A R Y

AMD

181

Am79C970A

SWITCHING CHARACTERISTICS: GPSI

Parameter

Symbol

Parameter Name

Test Condition

Min

Max

Unit

Transmit Timing

tGPT1

TXCLK Period (802.3 Compliant)

@ 1.5 V

99.99

100.01

tGPT2

TXCLK HIGH Time

@ 2.0 V

tGPT3

TXDAT and TXEN Delay from

@ 1.5 V

↑ TXCLK

tGPT4

RXEN Setup Before

@ 1.5 V

210

↑ TXCLK (Last Bit)

tGPT5

RXEN Hold After

↓ TXEN

@ 1.5 V

tGPT6

CLSN Active Time to Trigger Collision

@ 1.5 V (Note 1)

110

tGPT7

CLSN Active to

↓ RXEN to

@ 1.5 V

Prevent LCAR Assertion

tGPT8

CLSN Active to

↓ RXEN for

@ 1.5 V

4.0

µs

SQE Heartbeat window

tGPT9

CLSN Active to

↑ RXEN for

@ 1.5 V

Normal Collision

Receive Timing

tGPR1

RXCLK Period

@ 1.5 V (Note 2)

120

tGPR2

RXCLK HIGH Time

@ 2.0 V (Note 2)

tGPR3

RXCLK LOW Time

@ 0.8 V (Note 2)

tGPR4

RXDAT and RXEN Setup to

↑ RXCLK

@ 1.5 V

tGPR5

RXDAT Hold after

↑ RXCLK

@ 1.5 V

tGPR6

RXEN Hold after

↓ RXCLK

@ 1.5 V

tGPR7

CLSN Active to First

↑ RXCLK

@ 1.5 V

(Collision Recognition)

tGPR8

CLSN Active to

↓ RXCLK

@ 1.5 V (Note 3)

51.2

µs

for Address Type Designation Bit

tGPR9

CLSN Setup to Last

↑ RXCLK for

@ 1.5 V

210

Collision Recognition

tGPR10

CLSN Active

@ 1.5 V

110

tGPR11

CLSN Inactive Setup to First

↑ RXCLK

@ 1.5 V

300

tGPR12

CLSN Inactive Hold to Last

↑ RXCLK

@ 1.5 V

300

Notes:

1. CLSN must be asserted for a continuous period of 110 ns or more. Assertion for less than 110 ns period may or may not

result in CLSN recognition.

2. RXCLK should meet jitter requirements of IEEE 802.3 specification.

3. CLSN assertion before 51.2

µs will be indicated as a normal collision. CLSN assertion after 51.2 µs will be considered as a

Late Receive Collision.

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