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AM79C960KC датащи(PDF) 67 Page - Advanced Micro Devices

номер детали AM79C960KC
подробное описание детали  PCnetTM-ISA Single-Chip Ethernet Controller
PDF  127 Pages
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C960KC датащи(HTML) 67 Page - Advanced Micro Devices

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P R E L I M I N A R Y
AMD
1-409
Am79C960
controller will store incoming
frame data.
Read/write accessible only when
STOP bit is set.
CSR24-25: Base Address of Receive Ring
Bit
Name
Description
31-24
RES
Reserved locations. Written as
zero and read as undefined.
23-0
BADR
Contains the base address of the
Receive Ring.
Read/write accessible only when
STOP bit is set.
CSR26-27: Next Receive Descriptor Address
Bit
Name
Description
31-24
RES
Reserved locations. Written as
zero and read as undefined.
23-0
NRDA
Contains the next RDRE address
pointer.
Read/write accessible only when
STOP bit is set.
CSR28-29: Current Receive Descriptor Address
Bit
Name
Description
31-24
RES
Reserved locations. Written as
zero and read as undefined.
23-0
CRDA
Contains the current RDRE ad-
dress pointer.
Read/write accessible only when
STOP bit is set.
CSR30-31: Base Address of Transmit Ring
Bit
Name
Description
31-24
RES
Reserved locations. Written as
zero and read as undefined.
23-0
BADX
Contains the base address of the
Transmit Ring.
Read/write accessible only when
STOP bit is set.
CSR32-33: Next Transmit Descriptor Address
Bit
Name
Description
31-24
RES
Reserved locations. Written as
zero and read as undefined.
23-0
NXDA
Contains the next TDRE address
pointer.
Read/write accessible only when
STOP bit is set.
CSR34-35: Current Transmit Descriptor Address
Bit
Name
Description
31-24
RES
Reserved locations. Written as
zero and read as undefined.
23-0
CXDA
Contains the current TDRE ad-
dress pointer.
Read/write accessible only when
STOP bit is set.
CSR36-37: Next Next Receive Descriptor Address
Bit
Name
Description
31-0
NNRDA
Contains the next next RDRE ad-
dress pointer.
Read/write accessible only when
STOP bit is set.
CSR38-39: Next Next Transmit Descriptor Address
Bit
Name
Description
31-0
NNXDA
Contains the next next TDRE ad-
dress pointer.
Read/write accessible only when
STOP bit is set.
CSR40-41: Current Receive Status and Byte
Count
Bit
Name
Description
31-24 CRST
Current Receive Status. This
field is a copy of bits 15:8 of
RMD1 of the current receive
descriptor.



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