AM53CF96JC datasheet(43/76 Pages) AMD

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P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

into the FIFO before issuing this command. This com-

mand will be terminated early in the following

situations:

s The SCSI Timeout Register times out

s The Target does not go to the Message Out Phase

following the Selection Phase

s The Target removes Command Phase early

s The Target does not go to the Command Phase

following the Message Out Phase

s The Target exits the Command Out Phase early

A Successful Operation/Service Request interrupt is

generated when this command is executed success-

fully.

Reselect with ATN3 Steps Command

(Command Code 47H/C7H)

The Queue Tag feature of the Select with

ATN3 com-

mand has been implemented in the Reselection com-

mand. Therefore, a Target reselecting an Initiator can

use the QTAG feature of

ATN3. Following Reselection,

one message byte and 2 bytes QTAG will be sent. The

three message bytes must be loaded into the FIFO be-

fore this command is issued if DMA is not enabled.

General Commands

No Operation Command

(Command Code 00H/80H)

The No Operation Command administers no operation,

therefore an interrupt is not generated upon completion.

This command is issued following the Reset Device

Command to clear the Command Register (CMDREG).

A No Operation Command in the DMA mode may be

used to verify the contents of the Start Transfer Count

the transfer count and a DMA No Operation Command

is issued, reading the Current Transfer Count Register

(CTCREG) will give the transfer count value.

Clear FIFO Command

(Command Code 01H/81H)

The Clear FIFO Command is used to initialize the FIFO

to the empty condition. The Current FIFO Register

(CFISREG) reflects the empty FIFO status and the bot-

tom of the FIFO is set to zero. No interrupt is generated

at the end of this command.

Reset Device Command

(Command Code 02H/82H)

The Reset Device Command immediately stops any de-

vice operation and resets all the functions of the device.

It returns the device to the disconnected state and it also

generates a hard reset. The Reset Device Command re-

mains on the top of the Command Register FIFO hold-

ing the device in the reset state until the No Operation

Command is loaded. The No Operation command

serves to enable the Command Register.

Reset SCSI Bus Command

(Command Code 03H/83H)

The Reset SCSI Bus Command forces the

RSTC signal

active for a period of 25

µs, and drives the chip to the

Disconnected state. An interrupt is not generated upon

command completion, however, if bit 6 is not disabled in

Control Register One (CNTLREG1), a SCSI reset inter-

rupt will be issued.

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