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AM53CF96JC датащи(PDF) 26 Page - Advanced Micro Devices |
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AM53CF96JC датащи(HTML) 26 Page - Advanced Micro Devices |
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26 / 76 page ![]() P R E L I M I N A R Y AMD 26 Am53CF94/Am53CF96 Target Receive Command Steps Internal State Interrupt Status Register (06H) Register (05H) Explanation Bits 2:0 (Hex) Bits 7:0 (Hex) 2 18 Received entire CDB; Initiator asserted ATN 1 18 Sequence halted during command transfer due to parity error; ATN asserted by Initiator 2 08 Received entire CDB 1 08 Sequence halted during command transfer due to parity error; check FIFO flags Target Disconnect Steps Internal State Interrupt Status Register (06H) Register (05H) Explanation Bits 2:0 (Hex) Bits 7:0 (Hex) 2 28 Disconnect steps fully executed; disconnected; bus is free 1 18 Two message bytes sent; sequence halted because Initiator asserted ATN 0 18 One message byte sent; sequence halted because Initiator asserted ATN Target Terminate Steps Internal State Interrupt Status Register (06H) Register (05H) Explanation Bits 2:0 (Hex) Bits 7:0 (Hex) 2 28 Terminate steps fully executed; disconnected; bus is free 1 18 Status and message bytes sent; sequence halted because Initiator asserted ATN 0 18 Status byte sent; sequence halted because Initiator asserted ATN |
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