AM53CF96JC datasheet(27/76 Pages) AMD

номер детали	AM53CF96JC

подробное описание детали	Enhanced SCSI-2 Controller (ESC)

PDF	76 Pages

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производитель	AMD [Advanced Micro Devices]

домашняя страница	http://www.amd.com

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P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

Synchronous Transfer Period Register (06H) Write

Synchronous Transfer Period Register

STPREG

Address: 06H

Type: Write

543

210

RES

STP4

STP3

STP2

STP1

STP0

xxx

Reserved

Synchronous Transfer Period 4:0

Reserved

17348B-25

The Synchronous Transfer Period Register (STPREG)

contains a 5-bit value indicating the number of clock cy-

cles each byte will take to be transferred over the SCSI

bus in synchronous mode. The minimum value allowed

is 4. The STPREG defaults to 5 clocks/byte after a hard

or soft reset.

STPREG – Bits 7:5 – RES – Reserved

STPREG – Bits 4:0 – STP 4:0 – Synchronous

Transfer Period 4:0

The STP 4:0 bits are programmed to specify the syn-

chronous transfer period or the number of clock cycles

for each byte transfer in the synchronous mode. The

minimum value for STP 4:0 is 4 clocks/byte. Missing

table entries follow the binary code.

Clocks/

STP4

STP3

STP2

STP1

STP0

Byte

01004

01106

01117

•

•••••

•

•••••

1111

0000

0001

0010

0011

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