PIC14000 datasheet(49/153 Pages) MICROCHIP

49 / 153 page

Preliminary

DS40122B-page 49

PIC14000

7.5.1

SLAVE MODE

In slave mode, the SCLx and SDAx pins must be

conﬁgured as inputs (TRISC<7:6> or TRISD<1:0> are

set). The I2C module will override the input state with

the output data when required (slave-transmitter).

When an address is matched or the data transfer from

address

match

received,

the

hardware

automatically will generate the acknowledge (ACK)

pulse, and then load the I2CBUF with the received

value in the I2CSR.

There are two conditions that will cause the I2C module

not to give this ACK pulse. These are if either (or both)

occur:

• the Buffer Full (BF), I2CSTAT<0>, bit was set

before the transfer was received, or

• the Overﬂow (I2COV), I2CCON<6> bit was set

before the transfer was received.

In this case, the I2CSR value is not loaded into the

I2CBUF, but the I2CIF bit is set. Table 7-2 shows what

happens when a data transfer byte is received, given

the status of the BF and I2COV bits. The shaded boxes

show the conditions where user software did not

properly clear the overﬂow condition. The BF ﬂag is

cleared by reading the I2CBUF register while the

I2COV bit is cleared through software.

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I2C speciﬁcation as well as the requirement of the I2C

module is shown in the AC timing speciﬁcations.

TABLE 7-2:

DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data Transfer

is Received

I2COV

I2CSR-> I2CBUF

Generate ACK Pulse

Set I2CIF bit

(I2C interrupt if enabled)

Yes

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