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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AX2000 датащи(PDF) 119 Page - Microsemi Corporation |
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AX2000 датащи(HTML) 119 Page - Microsemi Corporation |
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119 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 2 - 105 Table 2-101 • Eight FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Units Parameter Description Min. Max. Min. Max. Min. Max. FIFO Module Timing tWSU Write Setup 15.46 17.61 20.70 ns tWHD Write Hold 0.00 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 0.75 ns tWCKL WCLK Low 5.13 5.13 5.13 ns tWCKP Minimum WCLK Period 5.88 5.88 5.88 ns tRSU Read Setup 16.22 18.47 21.72 ns tRHD Read Hold 0.00 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 0.73 ns tRCKL RCLK Low 5.77 5.77 5.77 ns tRCKP Minimum RCLK period 6.50 6.50 6.50 ns tCLRHF Clear High 0.00 0.00 0.00 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.92 2.18 2.57 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.39 5.00 5.88 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.13 2.42 2.85 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 5.04 5.75 6.75 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 3.39 3.86 4.54 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 4.93 5.62 6.61 ns Note: Timing data for these eight cascaded FIFO blocks uses a depth of 32,768. For all other combinations, use Microsemi’s timing software. |
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