AX2000 datasheet(116/262 Pages) MICROSEMI

номер детали	AX2000

подробное описание детали	Axcelerator Family FPGAs

PDF	262 Pages

Scroll/Zoom	100%

производитель	MICROSEMI [Microsemi Corporation]

домашняя страница	http://www.microsemi.com

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Detailed Specifications

2- 10 2

R ev isio n 1 8

Table 2-98 • One FIFO Block

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C

–2 Speed

–1 Speed

Std Speed

Units

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

FIFO Module Timing

tWSU

Write Setup

11.40

12.98

15.26

tWHD

Write Hold

0.22

0.25

0.30

tWCKH

WCLK High

0.75

tWCKL

WCLK Low

0.88

tWCKP

Minimum WCLK Period

1.63

tRSU

Read Setup

11.63

13.25

15.58

tRHD

Read Hold

0.00

tRCKH

RCLK High

0.77

tRCKL

RCLK Low

0.93

tRCKP

Minimum RCLK period

1.70

tCLRHF

Clear High

0.00

tCLR2FF

Clear-to-flag (EMPTY/FULL)

1.92

2.18

2.57

tCLR2AF

Clear-to-flag (AEMPTY/AFULL)

4.39

5.00

5.88

tCK2FF

Clock-to-flag (EMPTY/FULL)

2.13

2.42

2.85

tCK2AF

Clock-to-flag (AEMPTY/AFULL)

5.04

5.75

6.75

tRCK2RD1

RCLK-To-OUT (Pipelined)

1.32

1.51

1.77

tRCK2RD2

RCLK-To-OUT (Non-Pipelined)

2.16

2.46

2.90

Note:

Timing data for this single block FIFO has a depth of 4,096. For all other combinations, use Microsemi’s timing

software.

AX2000 датащи(PDF) 116 Page - Microsemi Corporation

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