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AX2000 датащи(PDF) 59 Page - Microsemi Corporation |
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AX2000 датащи(HTML) 59 Page - Microsemi Corporation |
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59 / 262 page ![]() Axcelerator Family FPGAs Re vi s i on 18 2 - 45 HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). The Axcelerator devices support Class I. This requires a differential amplifier input buffer and a push-pull output buffer. AC Loadings Timing Characteristics Table 2-41 • DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min., V Max., V Min., V Max., V Max., V Min., V mA mA -0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCC – 0.4 8 -8 Figure 2-20 • AC Test Loads Table 2-42 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF –0.5 VREF + 0.5 VREF 0.75 20 Note: * Measuring Point = VTRIP Test Point 20 pF 50 VTT Table 2-43 • 1.5 V HSTL Class I I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 1.425 V, TJ = 70°C –2 Speed –1 Speed Std Speed Units Parameter Description Min. Max. Min. Max. Min. Max. 1.5 V HSTL Class I I/O Module Timing tDP Input Buffer 1.80 2.05 2.41 ns tPY Output Buffer 4.90 5.58 6.56 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the I/O output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns |
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