PIC16 datasheet(58/418 Pages) MICROCHIP

58 / 418 page

PIC16(L)F1508/9

DS40001609C-page 58

 2011-2013 Microchip Technology Inc.

5.5

Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator or

external clock fail. If an oscillator mode is selected, the

FSCM can detect oscillator failure any time after the

Oscillator Start-up Timer (OST) has expired. When an

external clock mode is selected, the FSCM can detect

failure as soon as the device is released from Reset.

FSCM is enabled by setting the FCMEN bit in the

Configuration Words. The FSCM is applicable to external

oscillator modes (LP, XT, HS) and external clock modes

(ECH, ECM, ECL, EXTRC) and the Secondary Oscillator

(SOSC).

FIGURE 5-9:

FSCM BLOCK DIAGRAM

5.5.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

monitoring falling clock edges and using LFINTOSC as a

time base. See Figure 5-9. Detection of a failed oscillator

will take 32 to 96 cycles of the LFINTOSC. Figure 5-10

shows a timing diagram of the FSCM module.

5.5.2

FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

CPU clock to an internal clock source and sets the OSFIF

bit of the PIR2 register. The internal clock source is

determined by the IRCF<3:0> bits in the OSCCON

When the OSFIF bit is set, an interrupt will be generated,

if the OSFIE bit in the PIE2 register is enabled. The user’s

firmware in the Interrupt Service Routine (ISR) can then

take steps to mitigate the problems that may arise from

the failed clock.

The system clock will continue to be sourced from the

internal clock source until the fail-safe condition has

been cleared, see Section 5.5.3 “Fail-Safe Condition

Clearing”.

5.5.3

FAIL-SAFE CONDITION CLEARING

When a Fail-Safe condition exists, the user must take

the following actions to clear the condition before

returning to normal operation with the external source.

The next sections describe how to clear the Fail-Safe

condition for specific clock selections (FOSC bits) and

clock switching modes (SCS bit settings).

5.5.3.1

External Oscillator with

SCS<1:0> = 00

When a Fail-Safe condition occurs with the FOSC bits

selecting external oscillator (FOSC<2:0> = HS, XT, LP)

and the clock switch has been selected to run from the

FOSC selection (SCS<1:0> = 00), the condition is

cleared by performing the following procedure.

When SCS<1:0> = 00 (Running from FOSC selection)

SCS<1:0> = 1x:

Change the SCS bits in the OSCCON register

to select the internal oscillator block. This resets

the OST timer and allows it to operate again.

OSFIF = 0:

Clear the OSFIF bit in the PIR2 register.

SCS<1:0> = 00:

Change the SCS bits in the OSCCON register

to select the FOSC Configuration Word clock

selection. This will start the OST. The CPU will

continue to operate from the internal oscillator

until the OST count is reached. When OST

expires, the clock module will switch to the

external oscillator and the Fail-Safe condition

will be cleared.

If the Fail-Safe condition still exists, the OSFIF bit will

again be set by hardware.

5.5.3.2

External Clock with SCS<1:0> = 00

When a Fail-Safe condition occurs with the FOSC bits

selecting external clock (FOSC<2:0> = ECH, ECM,

ECL, EXTRC) and the clock switch has selected to run

from the FOSC selection (SCS<1:0> = 00), the condi-

tion is cleared by performing the following procedure.

When SCS<1:0> = 00 (Running from FOSC selection)

SCS<1:0> = 1x:

Change the SCS bits in the OSCCON register

to select the internal oscillator block. This resets

the OST timer and allows it to operate again.

OSFIF = 0:

Clear the OSFIF bit in the PIR2 register.

External

LFINTOSC

÷ 64

31 kHz

(~32

s)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

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