PIC12F635ESS datasheet(148/234 Pages) MICROCHIP

148 / 234 page

PIC12F635/PIC16F636/639

DS41232D-page 146

FIGURE 12-10:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

12.13 Code Protection

the

code

protection

bit(s)

have

not

been

programmed, the on-chip program memory can be

read out using ICSP for verification purposes.

12.14 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution but are

readable and writable during Program/Verify mode.

Only the Least Significant 7 bits of the ID locations are

used.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC + 1

PC + 2

Inst(PC) = Sleep

Inst(PC – 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy Cycle

PC + 2

0004h

0005h

Dummy Cycle

TOST(2)

PC + 2

Note

XT, HS or LP Oscillator mode assumed.

TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.

GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.

CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

Interrupt Latency(3)

Note:

The entire data EEPROM and Flash pro-

gram memory will be erased when the

code protection is turned off. See the

“PIC12F6XX/16F6XX Memory Program-

ming Specification” (DS41204) for more

information.

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