AD7738 datasheet(3/28 Pages) AD

3 / 28 page

REV. 0

AD7738

–3–

Parameter

Min

Typ

Max

Unit

Test Conditions/Comment

LOGIC INPUTS

SCLK, DIN,

CS, and RESET Inputs

Input Current

±1

µA

Input Current

±10

µA

CS = AV

–40

µA

Internal Pull-Up Resistor

Input Capacitance

VT+

1.4

DVDD = 5 V

VT–

0.8

1.4

DVDD = 5 V

VT+ – VT–

0.3

0.85

DVDD = 5 V

VT+

0.95

DVDD = 3 V

VT–

0.4

1.1

DVDD = 3 V

VT+ – VT–

0.3

0.85

DVDD = 3 V

MCLK IN Only

Input Current

±10

µA

Input Capacitance

VINL Input Low Voltage

0.8

DVDD = 5 V

VINH Input High Voltage

3.5

DVDD = 5 V

VINL Input Low Voltage

0.4

DVDD = 3 V

VINH Input High Voltage

2.5

DVDD = 3 V

LOGIC OUTPUTS

MCLKOUT

10, DOUT,

RDY

VOL Output Low Voltage

0.4

ISINK = 800

µA, DVDD = 5 V

VOH Output High Voltage

4.0

ISOURCE = 200

µA, DV

DD = 5 V

VOL Output Low Voltage

0.4

ISINK = 100

µA, DV

DD = 3 V

VOH Output High Voltage

DVDD – 0.6

ISOURCE = 100

µA, DV

DD = 3 V

Floating State Leakage Current

±1

µA

Floating State Leakage Capacitance

P1 INPUT

Levels Referenced to Analog Supplies

Input Current

±10

µA

VINL Input Low Voltage

0.8

AVDD = 5 V

VINH Input High Voltage

3.5

AVDD = 5 V

P0, P1 OUTPUT

VOL Output Low Voltage

0.4

ISINK = 8 mA, TMAX = 70

°C, AV

DD = 5 V

0.4

ISINK = 5 mA, TMAX = 85

°C, AV

DD = 5 V

0.4

ISINK = 2.5 mA, TMAX = 105

°C, AV

DD = 5 V

VOH Output High Voltage

4.0

ISOURCE = 200

µA, AV

DD = 5 V

POWER REQUIREMENTS

AVDD – AGND Voltage

4.75

5.25

DVDD – DGND Voltage

4.75

5.25

2.70

3.60

AVDD Current (Normal Mode)

13.6

AVDD = 5 V

AVDD Current (Internal Buffer Off )

8.5

AVDD = 5 V

DVDD Current (Normal Mode)

2.7

DVDD = 5 V

DVDD Current (Normal Mode)

1.0

1.5

DVDD = 3 V

AVDD + DVDD Current (Standby Mode)

µAAV

DD = DVDD = 5 V

Power Dissipation (Normal Mode)

100

Power Dissipation (Standby Mode)

500

µWAV

DD = DVDD = 5 V

NOTES

1Specifications are not production tested, but guaranteed by design and/or characterization data at initial product release.

2Specifications before calibration. Channel System Calibration reduces these errors to the order of the noise.

3Applies after the Zero Scale and Full-Scale calibration. The Negative Full Scale error represents the remaining error after removing the offset and gain error.

4Specifications before calibration. ADC Zero Scale Self-Calibration or Channel Zero Scale System Calibration reduces this error to the order of the noise.

5The output data span corresponds to the Nominal (Typical) Input Voltage Range. Correct operation of the ADC is guaranteed within the specified min/max.

Outside the Nominal Input Voltage Range, the OVR bit in the Channel Status register is set and the Channel Data register value depends on CLAMP bit in the

Mode register. See the register description and circuit description for more details.

6If chopping is enabled or when switching between channels, there will be a dynamic current charging the capacitance of the multiplexer, capacitance of the pins,

and any additional capacitance connected to the MUXOUT. See the circuit description for more details.

7For specified performance. Part is functional with Lower V

REF

8Dynamic current charging the sigma-delta modulator input switching capacitor.

9Outside the specified calibration range, calibration is possible but the performance may degrade.

10These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.

11With external MCLK, MCLKOUT disabled (CLKDIS bit set in the Mode register).

12External MCLKIN = 0 V or DV

DD, Digital Inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD.

Specifications are subject to change without notice.

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