Detailed Description

LVDS is intended for point-to-point communication over

a controlled-impedance medium as defined by the

ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS

uses a lower voltage swing than other common com-

munication standards, achieving higher data rates with

reduced power consumption while reducing EMI emis-

sions and system susceptibility to noise.

The MAX9130 is a single LVDS line receiver ideal for

applications requiring high data rates, low power, and

low noise. The device accepts an LVDS input and

translates it to an LVTTL/LVCMOS output. The receiver

detects differential signals as low as 50mV and as high

as 1V within an input voltage range of 0 to +2.4V.

The 250mV to 450mV differential output of an LVDS dri-

ver is nominally centered around a +1.25V offset. This

offset, coupled with the receiver’s 0 to +2.4V input volt-

age range, allows an approximate ±1V shift in the sig-

nal (as seen by the receiver). This allows for a

difference in ground references of the driver and the

receiver, the common-mode effects of coupled noise,

or both. The LVDS standards specify an input voltage

range of 0 to +2.4V referenced to receiver ground.

Fail-Safe

The fail-safe feature of the MAX9130 sets the output

high and reduces supply current to 150µA when:

• inputs are open

• inputs are undriven and shorted

• inputs are undriven and terminated

A fail-safe circuit is important because under these

conditions, noise at the input may switch the receiver

and it may appear to the system that data is being

received. Open or undriven terminated input conditions

can occur when a cable is disconnected or cut, or

when an LVDS driver output is in high impedance. A

short condition can occur because of a cable failure.

The fail-safe input network (Figure 1) samples the input

(nominal). When the input is driven to levels specified in

the LVDS standards, the input common-mode voltage

activated. If the inputs are open or if the inputs are

undriven and shorted or undriven and parallel terminat-

ed, there is no input current. In this case, a pullup resis-

0.3V, activating the fail-safe circuit and forcing the out-

put high.

Applications Information

Power-Supply Bypassing

ceramic 0.01µF capacitor as close to the device as

possible.

Single 500Mbps LVDS Line Receiver in SC70

6

_______________________________________________________________________________________

Pin Description

PIN

NAME

FUNCTION

GND with a 0.01µF ceramic capacitor.

2, 5

GND

Ground

3

IN-

Inverting LVDS Differential Input

4

IN+

Noninverting LVDS Differential Input

6

OUT

LVTTL/LVCMOS Output

IN+

IN-

GND

OUT

MAX9130

Figure 1. Fail-Safe Input Network

MAX9130

PULSE

GENERATOR

OUT

*50

Ω REQUIRED FOR PULSE GENERATOR.

IN+

IN-

*50

Ω

*50

Ω

Rx

Figure 2. Propagation Delay and Transition Time Test Circuit