Differential Traces

Input trace characteristics affect the performance of the

MAX9130. Use controlled-impedance PC board traces,

typically 100

Ω. Match the termination resistor to this

characteristic impedance.

Eliminate reflections and ensure that noise couples as

common mode by running the differential traces close

together. Reduce skew by matching the electrical

length of the traces. Excessive skew can result in a

degradation of magnetic field cancellation.

Input differential signals should be routed close to each

other to cancel their external magnetic field. Maintain a

constant distance between the differential traces to

avoid discontinuities in differential impedance. Minimize

the number of vias to further prevent impedance dis-

continuities.

Cables and Connectors

Transmission media should typically have a controlled

differential impedance of 100

Ω. Use cables and con-

nectors that have matched differential impedance to

minimize impedance discontinuities.

Avoid the use of unbalanced cables such as ribbon or

simple coaxial cable. Balanced cables such as twisted

pair offer superior signal quality and tend to generate

less EMI due to canceling effects. Balanced cables

tend to pick up noise as common mode, which is

rejected by the LVDS receiver.

Termination

The MAX9130 requires an external termination resistor.

The termination resistor should match the differential

impedance of the transmission line. Termination resis-

tance is typically 100

Ω but may range between 90Ω to

132

Ω, depending on the characteristic impedance of

the transmission medium.

When using the MAX9130, minimize the distance

between the input termination resistor and the MAX9130

receiver inputs. Use 1% surface-mount resistors.

Board Layout

For LVDS applications, use a four-layer PC board that

provides separate layers for power, ground, and

input/output signals is recommended. Keep the LVDS

input signals away from the output LVCMOS/LVTTL sig-

nal to prevent coupling (Figure 4). To minimize

crosstalk, do not run the output in parallel with the

inputs.

Chip Information

TRANSISTOR COUNT: 201

PROCESS: CMOS

Single 500Mbps LVDS Line Receiver in SC70

_______________________________________________________________________________________

7

20%

20%

50%

50%

80%

80%

Figure 3. Propagation Delay and Transition Time Waveforms

U1

R1

U1: MAX9130

R1, C1 ARE 0402 TYPE

IN-

(LVDS

INPUTS)

OUT

IN+

GND

GND

(LVTTL/LVCMOS OUTPUT)

C1

0.01

µF

Figure 4. Board Layout