MPC8548ECHXATHA datasheet(19/151 Pages) FREESCALE

19 / 151 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the device. The following table provides the RESET initialization AC timing specifications for the DDR

SDRAM component(s).

The following table provides the PLL lock times.

5.1

Power-On Ramp Rate

This section describes the AC electrical specifications for the power-on ramp rate requirements.

Controlling the maximum power-on ramp rate is required to avoid falsely triggering the ESD circuitry. The

following table provides the power supply ramp rate specifications.

Table 8. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET

100

—

s—

Minimum assertion time for SRESET

—

SYSCLKs

PLL input setup time with stable SYSCLK before HRESET negation

100

—

s—

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET

—

SYSCLKs

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET

—

SYSCLKs

Maximum valid-to-high impedance time for actively driven POR configs with

respect to negation of HRESET

—

SYSCLKs

Note:

1. SYSCLK is the primary clock input for the device.

Table 9. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Core and platform PLL lock times

—

100

s

Local bus PLL lock time

—

s

PCI/PCI-X bus PLL lock time

—

s

Table 10. Power Supply Ramp Rate

Parameter

Min

Max

Unit

Notes

Required ramp rate for MVREF

—

3500

V/s

Required ramp rate for VDD

—

4000

V/s

1, 2

Note:

1. Maximum ramp rate from 200 to 500 mV is most critical as this range may falsely trigger the ESD circuitry.

2. VDD itself is not vulnerable to false ESD triggering; however, as per Section 22.2, “PLL Power Supply Filtering,” the

recommended AVDD_CORE, AVDD_PLAT, AVDD_LBIU, AVDD_PCI1 and AVDD_PCI2 filters are all connected to VDD.

Their ramp rates must be equal to or less than the VDD ramp rate.

MPC8548ECHXATHA датащи(PDF) 19 Page - Freescale Semiconductor, Inc

MPC8548ECHXATHA датащи(HTML) 19 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL