MPC8548ECHXATHA datasheet(22/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

DDR and DDR2 SDRAM

6.2

DDR SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface. The DDR

controller supports both DDR1 and DDR2 memories. DDR1 is supported with the following AC timings

at data rates of 333 MHz. DDR2 is supported with the following AC timings at data rates down to

333 MHz.

6.2.1

DDR SDRAM Input AC Timing Specifications

This table provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 1.8 V.

Table 17 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5 V.

This table provides the input AC timing specifications for the DDR SDRAM interface.

Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions

Parameter

Symbol

Min

Max

Unit

AC input low voltage

VIL

—MVREF – 0.25

AC input high voltage

VIH

MVREF + 0.25

—

Table 17. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions.

Parameter

Symbol

Min

Max

Unit

AC input low voltage

VIL

—MVREF – 0.31

AC input high voltage

VIH

MVREF + 0.31

—

Table 18. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions.

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for MDQS—MDQ/MECC

533 MHz

400 MHz

333 MHz

tCISKEW

–300

–365

–390

300

365

390

1, 2

Notes:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

is captured with MDQS[n]. This must be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the following equation: tDISKEW = ± (T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the

absolute value of tCISKEW.

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