07XSC200 datasheet(35/51 Pages) FREESCALE

35 / 51 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

07XSC200

5.3.6

Ground Disconnect Protection

In the event the 07XSC200 ground is disconnected from load ground, the device protects itself and safely turns OFF the output,

regardless of the state of the output at the time of disconnection (maximum VPWR = 16 V). A 10 k resistor needs to be added

between the MCU and each digital input pin to ensure the device turns off, during a ground disconnect and to prevent this pin

from exceeding maximum ratings.

5.3.7

Loss of Supply Lines

5.3.7.1

Loss of VDD

If the external VDD supply is disconnected (or not within specification: VDD < VDD(FAIL), with the VDD_FAIL_en bit set to logic [1]),

all SPI register content is reset.

The outputs can still be driven by the direct inputs IN[0:1] if VPWR is within specified voltage range. The 07XSC200 uses the

battery input to power the output MOSFET-related current sense circuitry and any other internal logic providing Fail-safe device

operation with no VDD supplied. In this state, the overtemperature, overcurrent, severe short-circuit, short to VPWR and OFF

OpenLoad circuitry are fully operational, with default values corresponding to all SPI bits are set to logic [0]. No current is

conducted from VPWR to VDD.

5.3.7.2

Loss of VPWR

If the external VPWR supply is disconnected (or not within specification), the SPI configuration, reporting, and daisy chain features

are provided for RSTB to set to logic [1] under VDD in nominal conditions. This fault condition can be diagnosed with UV fault in

SPI STATR_s registers. The SPI pull-up and pull-down current sources are not operational. The previous device configuration

is maintained. No current is conducted from VDD to VPWR.

5.3.7.3

Loss of VPWR and VDD

If the external VPWR and VDD supplies are disconnected (or not within specification: (VDD and VPWR) < VSUPPLY(POR)), all SPI

register contents are reset, with default values corresponding to all SPI bits set to logic [0] and all latched faults reset.

5.3.8

EMC Performances

All following tests are performed on the Freescale evaluation board in accordance with the typical application schematic.

The device is protected in the event of positive and negative transients on the VPWR line (per ISO 7637-2).

The 07XSC200 successfully meets the Class 5 of the CISPR25 emission standard and 200 V/m or BCI 200 mA injection level

for immunity tests.

5.4

Logic Commands and Registers

5.4.1

Serial Input Communication

SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15

and ending with the LSB, D0 (Table 9). Each incoming command message on the SI pin can be interpreted using the following

bit assignments: the MSB, D15, is the watchdog bit (WDIN). In some cases, output selection is done with bit D13. The next four

bits, D14-D12:D10, are used to select the command register. The remaining nine bits, D8:D0, are used to configure and control

the outputs and their protection features.

Multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to

confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is

not 16 bits will be ignored.

The 07XSC200 has defined registers, which are used to configure the device and to control the state of the outputs. Table 10

summarizes the SI registers.

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