DSPIC33FJ06GS101TESLASHML datasheet(49/346 Pages) MICROCHIP

49 / 346 page

Preliminary

DS70318D-page 47

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

4.2.5

X AND Y DATA SPACES

The core has two data spaces, X and Y. These data

spaces can be considered either separate (for some

DSP instructions), or as one unified linear address

range (for MCU instructions). The data spaces are

accessed using two Address Generation Units (AGUs)

and separate data paths. This feature allows certain

instructions to concurrently fetch two words from RAM,

thereby enabling efficient execution of DSP algorithms,

such as Finite Impulse Response (FIR) filtering and

Fast Fourier Transform (FFT).

The X data space is used by all instructions and

supports all addressing modes. X data space has

separate read and write data buses. The X read data

bus is the read data path for all instructions that view

data space as combined X and Y address space. It is

also the X data prefetch path for the dual operand DSP

instructions (MAC class).

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,

EDAC, MAC, MOVSAC, MPY, MPY.N

and MSC) to

provide two concurrent data read paths.

Both the X and Y data spaces support Modulo

Addressing mode for all instructions, subject to

addressing mode restrictions. Bit-Reversed Addressing

mode is only supported for writes to X data space.

All data memory writes, including in DSP instructions,

view data space as combined X and Y address space.

The boundary between the X and Y data spaces is

device-dependent and is not user-programmable.

All effective addresses are 16 bits wide and point to

bytes within the data space. Therefore, the data space

address range is 64 Kbytes, or 32K words, though the

implemented memory locations vary by device.

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