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AM3703CUS датащи(PDF) 256 Page - Texas Instruments |
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AM3703CUS датащи(HTML) 256 Page - Texas Instruments |
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256 / 280 page ![]() AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED AUGUST 2011 www.ti.com Table 6-123. MMC1 Interface Switching Characteristics —High-Speed MMC Mode(4) (8) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC1 tc(clk) Frequency(1), output clk period 48 24 MHz MMC2 tW(clkH) Typical pulse duration, output clk high X(6)*PO(2) X(6)*PO(2) ns MMC2 tW(clkL) Typical pulse duration, output clk low Y(7)*PO(2) Y(7)*PO(2) ns tdc(clk) Duty cycle error, output clk 1041.7 2083.3 ps tJ(clk) Jitter standard deviation(3), output clk 200 200 ps MMC1 Interface (1.8-V IO) tR(clk) Rise time, output clk 3 3 ns tF(clk) Fall time, output clk 3 3 ns tR(data) Rise time, output data 3 3 ns tF(data) Fall time, output data 3 3 ns MMC5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd 3.7 14.1 4.1 34.5 ns transition MMC6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_dat[n:0](5) transition MMC1 Interface (3.0-V IO) tR(clk) Rise time, output clk 3 3 ns tF(clk) Fall time, output clk 3 3 ns tR(data) Rise time, output data 3 3 ns tF(clk) Fall time, output data 3 3 ns MMC5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to mmc1_cmd 3.7 14.1 4.1 34.5 ns transition MMC6 td(CLKOH-DATx) Delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_dat[n:0](5) transition (1) Related with the output clock maximum and minimum frequencies programmable in MMC module. (2) PO = output clock period in ns (3) The jitter probability density can be approximated by a Gaussian function. (4) Corresponding figures showing timing parameters are common with the Standard MMC mode figures. (5) In MMC1_dat[n:0], n is equal to 3. (6) The X parameter is defined as follows: CLKD X 1 or Even 0.5 Odd (trunk[CLKD/2]+1)/CLKD All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). (7) The Y parameter is defined as follows: CLKD Y 1 or Even 0.5 Odd (trunk[CLKD/2])/CLKD All required details about clock division factor CLKD can be found in the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). (8) See Section 4.3.4, Processor Clocks. 256 Timing Requirements and Switching Characteristics Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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