AM3703CUS datasheet(191/280 Pages) TI

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AM3715, AM3703

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SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

6.5.1.2

Parallel Camera Interface (CPI)

6.5.1.2.1 CPI

—Video and Graphics Digitizer 1.8V Mode

The imaging subsystem deals with the processing of the pixel data coming from an external image sensor

or from video and graphics digitizer. It is a key component for the following multimedia applications: video

preview, camera viewfinder, video record and still image capture. It supports RAW, RGB, and YUV data

processing.

Table 6-24 assumes testing over the recommended operating conditions and electrical characteristic

conditions below (see Figure 6-23 and Figure 6-24).

Table 6-23. CPI Timing Conditions

—Video and Graphics Digitizer 1.8-V Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

MIN

MAX

Input Conditions

Input signal rise time

1800

Input signal fall time

1800

Table 6-24. CPI Timing Requirements

—Video and Graphics Digitizer 1.8-V Mode(4) (6)

NO.

PARAMETER

OPP100

UNIT

MIN

MAX

ISP1

1 / tc(pclk)

Frequency(1), input pixel clock cam_pclk

148.5

MHz

ISP2

tw(pclkL)

Typical pulse duration, input pixel clock cam_pclk low

0.5P(2)

ISP3

tw(pclkH)

Typical pulse duration, input pixel clock cam_pclk high

0.5P(2)

tdc(pclk)

Duty cycle error, input pixel clock cam_pclk

0.5*P(2) -

3.247

tJ(pclk)

Cycle jitter(3), input pixel clock cam_pclk

0.06P(2)

ISP4

tsu(vsV-pclkH)

Setup time, input vertical synchronization cam_vs valid before input

0.75

pixel clock cam_pclk rising/falling edge

ISP5

th(pclkH-vsV)

Hold time, input vertical synchronization cam_vs valid after input pixel

0.96

clock cam_pclk rising/falling edge

ISP6

tsu(hsV-pclkH)

Setup time, input horizontal synchronization cam_hs valid before input

0.75

pixel clock cam_pclk rising/falling edge

ISP7

th(pclkH-hsV)

Hold time, input horizontal synchronization cam_hs valid after input

0.96

pixel clock cam_pclk rising/falling edge

ISP8

tsu(dV-pclkH)

Setup time, input data cam_d[n:0](5) valid before input pixel clock

0.75

cam_pclk rising/falling edge

ISP9

th(pclkH-dV)

Hold time, input data cam_d[n:0](5) valid after input pixel clock

0.96

cam_pclk rising/falling edge

ISP10

tsu(wenV-pclkH)

Setup time, input write enable cam_wen valid before input pixel clock

0.75

cam_pclk rising/falling edge

ISP11

th(pclkH-wenV)

Hold time, input write enable cam_wen valid after input pixel clock

0.96

cam_pclk rising/falling edge

ISP12

tsu(fldV-pclkH)

Setup time, input field identification cam_fld valid before input pixel

0.75

clock cam_pclk rising/falling edge

ISP13

th(pclkH-fldV)

Hold time, input field identification cam_fld valid after input pixel clock

0.96

cam_pclk rising/falling edge

(1) Related with the input maximum frequency supported by the ISP module in 8-bit mode with 8 to 16 data bits conversion bridge enabled.

(2) P = cam_pclk period in ns

(3) Maximum cycle jitter supported by cam_pclk input clock

(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.

(5) n = 11 (Data bus size is limited to 8 bits. So the bits configuration is either cam_d[7:0] or cam_d[11:4]). Lines not connected must be

tied low.

(6) See Section 4.3.4, Processor Clocks.

Timing Requirements and Switching Characteristics

191

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