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AM3703CUS датащи(PDF) 179 Page - Texas Instruments

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номер детали AM3703CUS
подробное описание детали  Sitara ARM Microprocessors
PDF  280 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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AM3703CUS датащи(HTML) 179 Page - Texas Instruments

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AM3715, AM3703
www.ti.com
SPRS616F
– JUNE 2010 – REVISED AUGUST 2011
Table 6-12. GPMC/NAND Flash Switching Characteristics
—Asynchronous Mode(15)
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
tR(d)
Rise time, output data gpmc_d[15:0]
2
2
ns
tF(d)
Fall time, output data gpmc_d[15:0]
2
2
ns
GNF0
tw(nweV)
Pulse duration, output write enable gpmc_nwe
A(1)
A(1)
ns
valid
GNF1
td(ncsV-nweV)
Delay time, output chip select gpmc_ncsx(13)
B(2)
– 0.2
B(2) + 2.0
B(2)
– 0.2
B(2) + 2.6
ns
valid to output write enable gpmc_nwe valid
GNF2
tw(cleH-nweV)
Delay time, output lower-byte
C(3)
– 0.2
C(3) + 2.0
C(3)
– 0.2
C(3) + 2.6
ns
enable/command latch enable gpmc_nbe0_cle
high to output write enable gpmc_nwe valid
GNF3
tw(nweV-dV)
Delay time, output data gpmc_d[15:0] valid to
D(4)
– 0.2
D(4) + 2.0
D(4)
– 0.2
D(4) + 2.6
ns
output write enable gpmc_nwe valid
GNF4
tw(nweIV-dIV)
Delay time, output write enable gpmc_nwe
E(5)
– 0.2
E(5) + 2.0
E(5)
– 0.2
E(5) + 2.6
ns
invalid to output data gpmc_d[15:0] invalid
GNF5
tw(nweIV-cleIV)
Delay time, output write enable gpmc_nwe
F(6)
– 0.2
F(6) + 2.0
F(6)
– 0.2
F(6) + 2.6
ns
invalid to output lower-byte enable/command
latch enable gpmc_nbe0_cle invalid
GNF6
tw(nweIV-ncsIV)
Delay time, output write enable gpmc_nwe
G(7)
– 0.2
G(7) + 2.0
G(7)
– 0.2
G(7) + 2.6
ns
invalid to output chip select gpmc_ncsx(13)
invalid
GNF7
tw(aleH-nweV)
Delay time, output address valid/address latch
C(3)
– 0.2
C(3) + 2.0
C(3)
– 0.2
C(3) + 2.6
ns
enable gpmc_nadv_ale high to output write
enable gpmc_nwe valid
GNF8
tw(nweIV-aleIV)
Delay time, output write enable gpmc_nwe
F(6)
– 0.2
F(6) + 2.0
F(6)
– 0.2
F(6) + 2.6
ns
invalid to output address valid/address latch
enable gpmc_nadv_ale invalid
GNF9
tc(nwe)
Cycle time, write
H(8)
H(8)
ns
GNF10
td(ncsV-noeV)
Delay time, output chip select gpmc_ncsx(13)
I(9)
– 0.2
I(9) + 2.0
I(9)
– 0.2
I(9) + 2.6
ns
valid to output enable gpmc_noe valid
GNF13
tw(noeV)
Pulse duration, output enable gpmc_noe valid
K(10)
K(10)
ns
GNF14
tc(noe)
Cycle time, read
L(11)
L(11)
ns
GNF15
tw(noeIV-ncsIV)
Delay time, output enable gpmc_noe invalid to
M(12)
– 0.2 M(12) + 2.0 M(12) – 0.2 M(12) + 2.6
ns
output chip select gpmc_ncsx(13) invalid
(1) A = (WEOffTime
– WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK(14)
(2) B = ((WEOnTime
– CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(3) C = ((WEOnTime
– ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK(14)
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay) * GPMC_FCLK(14)
(5) E = ((WrCycleTime
– WEOffTime) * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay) * GPMC_FCLK(14)
(6) F = ((ADVWrOffTime
– WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay)) * GPMC_FCLK(14)
(7) G = ((CSWrOffTime
– WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay)) * GPMC_FCLK(14)
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK(14)
(9) I = ((OEOnTime
– CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK(14)
(10) K = (OEOffTime
– OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK(14)
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK(14)
(12) M = ((CSRdOffTime
– OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay)) * GPMC_FCLK(14)
(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) See Section 4.3.4, Processor Clocks.
Copyright
© 2010–2011, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics
179
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Product Folder Link(s): AM3715 AM3703



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