AM3703CUS datasheet(161/280 Pages) TI

161 / 280 page

AM3715, AM3703

www.ti.com

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

Table 6-4. GPMC/NOR Flash Switching Characteristics

—Synchronous Mode(2) (18) (continued)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

tdc(clk)

Duty cycle error, output clock gpmc_clk

–500

500

–500

500

tJ(clk)

Jitter standard deviation(16), output clock gpmc_clk

33.33

tR(clk)

Rise time, output clock gpmc_clk

1.6

tF(clk)

Fall time, output clock gpmc_clk

1.6

tR(do)

Rise time, output data gpmc_d[15:0]

tF(do)

Fall time, output data gpmc_d[15:0]

td(clkH-ncsV)

Delay time, output clock gpmc_clk rising edge to

F(6)

– 1.9

F(6) + 3.3

F(6)

– 1.9

F(6) + 3.3

output chip select gpmc_ncsx(11) transition

td(clkH-ncsIV)

Delay time, output clock gpmc_clk rising edge to

E(5)

– 1.9 E(5) + 3.3 E(5) – 1.9 E(5) + 3.3

output chip select gpmc_ncsx(11) invalid

td(aV-clk)

Delay time, output address gpmc_a[27:1] valid to

B(2)

– 4.1 B(2) + 2.1 B(2) – 4.1 B(2) + 2.1

output clock gpmc_clk first edge

td(clkH-aIV)

Delay time, output clock gpmc_clk rising edge to

–2.1

output address gpmc_a[27:1] invalid

td(nbeV-clk)

Delay time, output lower byte enable/command latch

B(2)

– 1.2 B(2) + 2.2 B(2) – 1.2 B(2) + 2.2

enable gpmc_nbe0_cle, output upper byte enable

gpmc_nbe1 valid to output clock gpmc_clk first edge

td(clkH-nbeIV)

Delay time, output clock gpmc_clk rising edge to

D(4)

– 2.2 D(4) + 1.2 D(4) – 2.2 D(4) + 1.2

output lower byte enable/command latch enable

gpmc_nbe0_cle, output upper byte enable gpmc_nbe1

invalid

td(clkH-nadv)

Delay time, output clock gpmc_clk rising edge to

G(7) + 0.8 G(7) + 2.2 G(7) + 0.8 G(7) + 2.2

output address valid/address latch enable

gpmc_nadv_ale transition

td(clkH-nadvIV)

Delay time, output clock gpmc_clk rising edge to

D(4)

– 1.9 D(4) + 4.1 D(4) – 1.9 D(4) + 4.1

output address valid/address latch enable

gpmc_nadv_ale invalid

F10

td(clkH-noe)

Delay time, output clock gpmc_clk rising edge to

H(8)

– 2.1 H(8) + 2.1 H(8) – 2.1 H(8) + 2.1

output enable gpmc_noe transition

F11

td(clkH-noeIV)

Delay time, output clock gpmc_clk rising edge to

E(5)

– 2.1 E(5) + 2.1 E(5) – 2.1 E(5) + 2.1

output enable gpmc_noe invalid

F14

td(clkH-nwe)

Delay time, output clock gpmc_clk rising edge to

I(9)

– 1.9

I(9) + 4.1

I(9)

– 1.9

I(9) + 4.1

output write enable gpmc_nwe transition

F15

td(clkH-do)

Delay time, output clock gpmc_clk rising edge to

J(10)

–

J(10) +

J(10)

–

J(10) +

output data gpmc_d[15:0] transition

1.7

1.2

1.7

1.2

F17

td(clkH-nbe)

Delay time, output clock gpmc_clk rising edge to

J(10)

–

J(10) +

J(10)

–

J(10) +

output lower byte enable/command latch enable

2.2

1.2

2.2

1.2

gpmc_nbe0_cle transition

F18

tw(ncsV)

Pulse duration, output chip select

Read

A(1)

gpmc_ncsx(11) low

Write

A(1)

F19

tw(nbeV)

Pulse duration, output lower byte

Read

C(3)

enable/command latch enable

Write

C(3)

gpmc_nbe0_cle, output upper byte enable

gpmc_nbe1 low

F20

tw(nadvV)

Pulse duration, output address

Read

K(13)

valid/address latch enable gpmc_nadv_ale

Write

K(13)

low

F23

td(clkH-iodir)

Delay time, output clock gpmc_clk rising edge to

H(8)

– 2.1 H(8) + 4.1 H(8) – 2.1 H(8) + 4.1

output IO direction control gpmc_io_dir high (IN

direction)

F24

td(clkH-iodirIV)

Delay time, output clock gpmc_clk rising edge to

M(17)

–

M(17) +

M(17)

–

M(17) +

output IO direction control gpmc_io_dir low (OUT

2.1

4.1

2.1

4.1

direction)

Timing Requirements and Switching Characteristics

161

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