MPC8306S datasheet(12/70 Pages) FREESCALE

12 / 70 page

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

RESET Initialization

4.2

AC Electrical Characteristics

The primary clock source for the MPC8306S is SYS_CLK_IN. The following table provides the clock

input (SYS_CLK_IN) AC timing specifications for the MPC8306S. These specifications are also

applicable for QE_CLK_IN.

RESET Initialization

This section describes the AC electrical specifications for the reset initialization timing requirements of

the MPC8306S. The following table provides the reset initialization AC timing specifications for the reset

component(s).

Table 8. SYS_CLK_IN AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Note

SYS_CLK_IN frequency

fSYS_CLK_IN

—

66.67

MHz

SYS_CLK_IN cycle time

tSYS_CLK_IN

—

41.6

—

SYS_CLK_IN rise and fall time

tKH, tKL

1.1

—

2.8

SYS_CLK_IN duty cycle

tKHK/tSYS_CLK_

—

SYS_CLK_IN jitter

—

±150

4, 5

Notes:

1. Caution: The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating

frequencies.

2. Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.

6. Spread spectrum is allowed up to 1% down-spread @ 33kHz (max rate).

Table 9. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Note

Required assertion time of HRESET to activate reset flow

—

tSYS_CLK_IN

Required assertion time of PORESET with stable clock applied to

SYS_CLK_IN

—

tSYS_CLK_IN

HRESET assertion (output)

512

—

tSYS_CLK_IN

Input setup time for POR configuration signals

(CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET

4—

tSYS_CLK_IN

1, 2

Input hold time for POR config signals with respect to negation of

HRESET

—

1, 2

Notes:

1. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8306S PowerQUICC

II Pro Integrated Communications Processor Family Reference Manual

2. POR configuration signals consist of CFG_RESET_SOURCE[0:3].

MPC8306S датащи(PDF) 12 Page - Freescale Semiconductor, Inc

MPC8306S датащи(HTML) 12 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

датащи скачать

ссылки URL