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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8306S датащи(PDF) 29 Page - Freescale Semiconductor, Inc |
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MPC8306S датащи(HTML) 29 Page - Freescale Semiconductor, Inc |
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29 / 70 page  MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 29 HDLC The following figure represents the AC timing from Table 27. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 19. TDM/SI AC Timing (External Clock) Diagram 10 HDLC This section describes the DC and AC electrical specifications for the high level data link control (HDLC), of the MPC8306S. 10.1 HDLC DC Electrical Characteristics The following table provides the DC electrical characteristics for the MPC8306S HDLC protocol. 10.2 HDLC AC Timing Specifications The following table provides the input and output AC timing specifications for HDLC protocol. Table 28. HDLC DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Output high voltage VOH IOH = –2.0 mA 2.4 — V Output low voltage VOL IOL = 3.2 mA — 0.5 V Input high voltage VIH —2.0 OVDD +0.3 V Input low voltage VIL —–0.3 0.8 V Input current IIN 0 V VIN OVDD — ±5 A Table 29. HDLC AC Timing Specifications1 Characteristic Symbol2 Min Max Unit Outputs—Internal clock delay tHIKHOV 09 ns Outputs—External clock delay tHEKHOV 1 12 ns Outputs—Internal clock high impedance tHIKHOX 05.5 ns TDM/SICLK (Input) tSEIXKH tSEIVKH tSEKHOV Input Signals: TDM/SI (See Note) Output Signals: TDM/SI (See Note) Note: The clock edge is selectable on TDM/SI. tSEKHOX |
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