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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8306SEC датащи(PDF) 27 Page - Freescale Semiconductor, Inc |
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MPC8306SEC датащи(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 70 page  MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 27 Ethernet and MII Management The following figure shows the MII management AC timing diagram. Figure 17. MII Management Interface Timing Diagram MDC to MDIO delay tMDKHDX 10 — 70 ns — MDIO to MDC setup time tMDDVKH 8.5 — — ns — MDIO to MDC hold time tMDDXKH 0— — ns — MDC rise time tMDCR — — 10 ns — MDC fall time tMDHF — — 10 ns — Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Table 25. MII Management AC Timing Specifications (continued) At recommended operating conditions with OVDD is 3.3 V ± 300mV. Parameter/Condition Symbol1 Min Typical Max Unit Note MDC tMDDXKH tMDC tMDCH tMDCR tMDCF tMDDVKH tMDKHDX MDIO MDIO (Input) (Output) |
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