AD1933

Data Sheet

Rev. E | Page 16 of 28

DLRCLK

DBCLK

DSDATA1

DAC L1

DAC R1

DAC L2

DAC R2

DSDATA2

DAC L3

DAC R3

DAC L4

DAC R4

32 BITS

MSB

Figure 14. Dual-Line, DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LSB

LSB

LSB

LSB

LSB

LSB

LEFT CHANNEL

RIGHT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

MSB

MSB

MSB

MSB

MSB

MSB

RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL

DSP MODE—16 BITS TO 24 BITS PER CHANNEL

LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL

LRCLK

BCLK

SDATA

LSB

LSB

NOTES

1. DSP MODE DOES NOT IDENTIFY CHANNEL.

2. LRCLK NORMALLY OPERATES AT

3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.

MSB

MSB

1/

Figure 15. Stereo Serial Modes