AD1933YSTZ datasheet(13/28 Pages) AD

13 / 28 page

Data Sheet

AD1933

Rev. E | Page 13 of 28

POWER SUPPLY AND VOLTAGE REFERENCE

The AD1933 is designed for 3.3 V supplies. Separate power

supply pins are provided for the analog and digital sections.

These pins should be bypassed with 100 nF ceramic chip

capacitors, as close to the pins as possible, to minimize noise

pickup. A bulk aluminum electrolytic capacitor of at least 22 μF

should also be provided on the same PCB as the DAC. For

critical applications, improved performance is obtained with

separate supplies for the analog and digital sections. If this is

not possible, it is recommended that the analog and digital

supplies be isolated by means of a ferrite bead in series with

each supply. It is important that the analog supply be as clean

as possible.

The AD1933 includes a 3.3 V regulator driver that only requires

an external pass transistor and bypass capacitors to make a 5 V

to 3.3 V regulator. If the regulator driver is not used, connect

VSUPPLY, VDRIVE, and VSENSE to DGND.

All digital inputs are compatible with TTL and CMOS levels.

All outputs are driven from the 3.3 V DVDD supply and are

compatible with TTL and 3.3 V CMOS levels.

The DAC internal voltage reference (VREF) is brought out on

FILTR and should be bypassed as close as possible to the chip,

with a parallel combination of 10 μF and 100 nF. Any external

current drawn should be limited to less than 50 μA.

The internal reference can be disabled in the PLL and Clock

Control 1 register and FILTR can be driven from an external

source. This can be used to scale the DAC output to the clipping

level of a power amplifier based on its power supply voltage,

DAC output gain is proportional to the FILTR voltage.

The CM pin is the internal common-mode reference. It should

be bypassed as close as possible to the chip, with a parallel

combination of 47 μF and 100 nF. This voltage can be used to

bias external op amps to the common-mode voltage of the input

and output signal pins. The output current should be limited to

less than 0.5 mA source and 2 mA sink.

SERIAL DATA PORTS—DATA FORMAT

The eight DAC channels use a common serial bit clock (DBCLK)

and a common left-right framing clock (DLRCLK) in the serial

data port. The clock signals are all synchronous with the sample

rate. The normal stereo serial modes are shown in Figure 15.

The DAC serial data modes default to I2S. The ports can also be

programmed for left-justified, right-justified, and TDM modes.

The word width is 24 bits by default and can be programmed

for 16 or 20 bits. The DAC serial formats are programmable

according to the DAC Control 0 register. The polarity of the

DBCLK and DLRCLK is programmable according to the DAC

Control 1 register. The auxiliary TDM port is also provided for

applications requiring more than eight DAC channels. In this

mode, the AUXTDMLRCLK and AUXTDMBCLK pins are

configured as TDM port clocks. In regular TDM mode, the

DLRCLK and DBCLK pins are used as the TDM port clocks.

The auxiliary TDM serial port format and its serial clock

polarity are programmable according to the Auxiliary TDM

Port Control 0 register and the Auxiliary TDM Port Control 1

programmable to become the bus masters according to the

DAC Control 1 register and auxiliary TDM Control 1 register.

By default, both auxiliary TDM and DAC serial ports are in

slave mode.

TIME-DIVISION MULTIPLEXED (TDM) MODES

The AD1933 serial ports have several different TDM serial data

modes. The most commonly used configuration is shown in

Figure 10. In Figure 10, the eight on-chip DAC data slots are

packed into one TDM stream. In this mode, DBCLK is 256 fS.

The I/O pins of the serial ports are defined according to the

serial mode selected. For a detailed description of the function

of each pin in TDM and auxiliary modes, see Table 11.

The AD1933 allows systems with more than eight DAC channels

to be easily configured by the use of an auxiliary serial data port.

The DAC TDM-AUX mode is shown in Figure 11. In this mode,

the AUX channels are the last four slots of the 16-channel TDM

data stream. These slots are extracted and output to the AUX

serial port. One major difference between the TDM mode and

an auxiliary TDM mode is the assignment of the TDM port

pins, as shown in Table 11. In auxiliary TDM mode, DBCLK

and DLRCLK are assigned as the auxiliary port clocks, and

AUXTDMBCLK and AUXTDMLRCLK are assigned as the

TDM port clocks. In regular TDM or 16-channel, daisy-chain

TDM mode, the DLRCLK and DBCLK pins are set as the TDM

port clocks.

It should be noted that due to the high AUXTDMBCLK

frequency, 16-channel auxiliary TDM mode is available only

in the 48 kHz/44.1 kHz/32 kHz sample rate.

SLOT 1

LEFT 1

SLOT 2

RIGHT 1

SLOT 3

LEFT 2

SLOT 4

RIGHT 2

MSB

MSB–1

MSB–2

DATA

BCLK

LRCLK

SLOT 5

LEFT 3

SLOT 6

RIGHT 3

SLOT 7

LEFT 4

SLOT 8

RIGHT 4

LRCLK

BCLK

DATA

256 BCLKs

32 BCLK

Figure 10. DAC TDM (8-Channel I2S Mode)

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