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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD1933YSTZ датащи(PDF) 6 Page - Analog Devices |
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AD1933YSTZ датащи(HTML) 6 Page - Analog Devices |
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6 / 28 page  AD1933 Data Sheet Rev. E | Page 6 of 28 TIMING SPECIFICATIONS −40°C < TC < +125°C, DVDD = 3.3 V ± 10%. Table 7. Parameter Condition Comments Min Max Unit INPUT MASTER CLOCK (MCLK) AND RESET tMH MCLK duty cycle DAC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, and 768 fS 40 60 % tMH DAC clock source = direct MCLK @ 512 fS (bypass on-chip PLL) 40 60 % fMCLK MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz fMCLK Direct 512 fS mode 27.6 MHz tPDR RST low 15 ns tPDRR RST recovery Reset to active output 4096 tMCLK PLL Lock Time MCLK and LR clock input 10 ms 256 fS VCO Clock, Output Duty Cycle MCLKO/XO Pin 40 60 % SPI PORT See Figure 9 tCCH CCLK high 35 ns tCCL CCLK low 35 ns fCCLK CCLK frequency fCCLK = 1/tCCP, only tCCP shown in Figure 9 10 MHz tCDS CIN setup To CCLK rising 10 ns tCDH CIN hold From CCLK rising 10 ns tCLS CLATCH setup To CCLK rising 10 ns tCLH CLATCH hold From CCLK rising 10 ns tCLHIGH CLATCH high Not shown in Figure 9 10 ns tCOE COUT enable From CCLK falling 30 ns tCOD COUT delay From CCLK falling 30 ns tCOH COUT hold From CCLK falling, not shown in Figure 9 30 ns tCOTS COUT tristate From CCLK falling 30 ns DAC SERIAL PORT See Figure 16 tDBH DBCLK high Slave mode 10 ns tDBL DBCLK low Slave mode 10 ns tDLS DLRCLK setup To DBCLK rising, slave mode 10 ns tDLH DLRCLK hold From DBCLK rising, slave mode 5 ns tDLS DLRCLK skew From DBCLK falling, master mode −8 +8 ns tDDS DSDATA setup To DBCLK rising 10 ns tDDH DSDATA hold From DBCLK rising 5 ns AUXTDM SERIAL PORT See Figure 17 tABH AUXTDMBCLK high Slave mode 10 ns tABL AUXTDMBCLK low Slave mode 10 ns tALS AUXTDMLRCLK setup To AUXTDMBCLK rising, slave mode 10 ns tALH AUXTDMLRCLK hold From AUXTDMBCLK rising, slave mode 5 ns tALS AUXTDMLRCLK skew From AUXTDMBCLK falling, master mode −8 +8 ns tDDS DSDATA setup To AUXTDMBCLK, not shown in Figure 17 10 ns tDDH DSDATA hold From AUXTDMBCLK rising, not shown in Figure 17 5 ns AUXILIARY INTERFACE tDXDD AUXDATA delay From AUXBCLK falling 18 ns tXBH AUXBCLK high 10 ns tXBL AUXBCLK low 10 ns tDLS AUXLRCLK setup To AUXBCLK rising 10 ns tDLH AUXLRCLK hold From AUXBCLK rising 5 ns |
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