AD9742ARURL7 datasheet(14/32 Pages) AD

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AD9742

Data Sheet

Rev. C | Page 14 of 32

The output impedance of IOUTA and IOUTB is determined by

the equivalent parallel combination of the PMOS switches

associated with the current sources and is typically 100 kΩ in

parallel with 5 pF. It is also slightly dependent on the output

voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS

device. As a result, maintaining IOUTA and/or IOUTB at a

virtual ground via an I-V op amp configuration will result in

the optimum dc linearity. Note that the INL/DNL specifications

for the AD9742 are measured with IOUTA maintained at a

virtual ground via an op amp.

IOUTA and IOUTB also have a negative and positive voltage

compliance range that must be adhered to in order to achieve

optimum performance. The negative output compliance range

of −1 V is set by the breakdown limits of the CMOS process.

Operation beyond this maximum limit may result in a breakdown

of the output stage and affect the reliability of the AD9742.

The positive output compliance range is slightly dependent on

the full-scale output current, IOUTFS. It degrades slightly from its

nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA.

The optimum distortion performance for a single-ended or

differential output is achieved when the maximum full-scale

signal at IOUTA and IOUTB does not exceed 0.5 V.

DIGITAL INPUTS

The AD9742 digital section consists of 12 input bit channels

and a clock input. The 12-bit parallel data inputs follow standard

positive binary coding, where DB11 is the most significant bit

(MSB) and DB0 is the least significant bit (LSB). IOUTA produces

a full-scale output current when all data bits are at Logic 1. IOUTB

produces a complementary output with the full-scale current

split between the two outputs as a function of the input code.

DVDD

DIGITAL

INPUT

Figure 25. Equivalent Digital Input

The digital interface is implemented using an edge-triggered

master/slave latch. The DAC output updates on the rising edge

of the clock and is designed to support a clock rate as high as

210 MSPS. The clock can be operated at any duty cycle that meets

the specified latch pulse width. The setup and hold times can

also be varied within the clock cycle as long as the specified

minimum times are met, although the location of these

transition edges may affect digital feedthrough and distortion

performance. Best performance is typically achieved when the

input data transitions on the falling edge of a 50% duty cycle clock.

CLOCK INPUT

SOIC/TSSOP Packages

The 28-lead package options have a single-ended clock input

(CLOCK) that must be driven to rail-to-rail CMOS levels. The

quality of the DAC output is directly related to the clock quality,

and jitter is a key concern. Any noise or jitter in the clock will

translate directly into the DAC output. Optimal performance

will be achieved if the CLOCK input has a sharp rising edge,

since the DAC latches are positive edge triggered.

LFCSP Package

A configurable clock input is available in the LFCSP package,

which allows for one single-ended and two differential modes.

The mode selection is controlled by the CMODE input, as

summarized in Table 7. Connecting CMODE to CLKCOM

selects the single-ended clock input. In this mode, the CLK+

input is driven with rail-to-rail swings and the CLK− input is

left floating. If CMODE is connected to CLKVDD, the differential

receiver mode is selected. In this mode, both inputs are high

impedance. The final mode is selected by floating CMODE. This

mode is also differential, but internal terminations for positive

emitter-coupled logic (PECL) are activated. There is no significant

performance difference between any of the three clock input modes.

Table 7. Clock Mode Selection

CMODE Pin

Clock Input Mode

CLKCOM

Single-Ended

CLKVDD

Differential

Float

PECL

The single-ended input mode operates in the same way as the

CLOCK input in the 28-lead packages, as described previously.

In the differential input mode, the clock input functions as a

high impedance differential pair. The common-mode level of

the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and

the differential voltage can be as low as 0.5 V p-p. This mode

can be used to drive the clock with a differential sine wave since

the high gain bandwidth of the differential inputs will convert

the sine wave into a single-ended square wave internally.

The final clock mode allows for a reduced external component

count when the DAC clock is distributed on the board using

PECL logic. The internal termination configuration is shown in

Figure 26. These termination resistors are untrimmed and can

vary up to ±20%. However, matching between the resistors

should generally be better than ±1%.

CLK+

TO DAC CORE

CLK–

VTT = 1.3V NOM

Ω

AD9742

CLOCK

RECEIVER

Figure 26. Clock Termination in PECL Mode\

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