Data Sheet

AD9742

Rev. C | Page 7 of 32

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

14

13

12

11

17

16

15

20

19

18

10

9

8

1

2

3

4

7

6

5

28

27

26

25

24

23

22

21

NC = NO CONNECT

DB7

DB6

DB5

DB4

DB3

DB2

DB1

(LSB) DB0

NC

NC

CLOCK

DVDD

DCOM

MODE

AVDD

RESERVED

IOUTA

IOUTB

ACOM

NC

FS ADJ

REFIO

REFLO

SLEEP

DB8

DB9

DB10

(MSB) DB11

AD9742

TOP VIEW

(Not to Scale)

Figure 3. 28-Lead SOIC and 28-Lead TSSOP Pin Configuration

24 FS ADJ

23 REFIO

22 ACOM

21 IOUTA

DB5 1

DB4 2

DVDD 3

20 IOUTB

19 ACOM

18 AVDD

17 AVDD

DB3 4

DB2 5

DB1 6

(LSB) DB0 7

NC 8

AD9742

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

NOTES

1. NC = NO CONNECT.

2. IT IS RECOMMENDED THAT THE EXPOSED PAD

BE THERMALLY CONNECTED TO A COPPER

GROUND PLANE FOR ENHANCED ELECTRICAL

AND THERMAL PERFORMANCE.

Figure 4. 32-Lead LFCSP Pin Configuration

Table 6. Pin Function Descriptions (N/A = Not Applicable)

SOIC/TSSOP

Pin No.

LFCSP

Pin No.

Mnemonic

Description

1

27

DB11

Most Significant Data Bit (MSB).

2 to 11

28 to 32,

1, 2, 4 to 6

DB10 to DB1

Data Bits 10 to 1.

12

7

DB0

Least Significant Data Bit (LSB).

13, 14

8, 9

NC

No Internal Connection.

15

25

SLEEP

Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left

unterminated if not used.

16

N/A

REFLO

Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal

reference.

17

23

REFIO

Reference Input/Output. Serves as reference input when internal reference disabled (that is, tie

REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (that is, tie

REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated.

18

24

FS ADJ

Full-Scale Current Output Adjust.

19

N/A

NC

No Internal Connection.

20

19, 22

ACOM

Analog Common.

21

20

IOUTB

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

22

21

IOUTA

DAC Current Output. Full-scale current when all data bits are 1s.

23

N/A

RESERVED

Reserved. Do not connect to common or supply.

24

17, 18

AVDD

Analog Supply Voltage (3.3 V).

25

16

MODE

Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.

N/A

15

CMODE

Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float

CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip).

26

10, 26

DCOM

Digital Common.

27

3

DVDD

Digital Supply Voltage (3.3 V).

28

N/A

CLOCK

Clock Input. Data latched on positive edge of clock.

N/A

12

CLK+

Differential Clock Input.

N/A

13

CLK−

Differential Clock Input.

N/A

11

CLKVDD

Clock Supply Voltage (3.3 V).

N/A

14

CLKCOM

Clock Common.

N/A

EPAD

It is recommended that the exposed pad be thermally connected to a copper ground plane for

enhanced electric and thermal performance.