AD7482

Rev. B | Page 17 of 20

BOARD LAYOUT AND GROUNDING

For optimum performance from the AD7482, it is recommended

that a PCB with a minimum of three layers be used. One of

these layers, preferably the middle layer, should be as complete a

ground plane as possible to give the best shielding. The board

should be designed in such a way that the analog and digital

circuitry is separated and confined to certain areas of the board.

This practice, along with not running digital and analog lines close

together, helps to avoid coupling digital noise onto analog lines.

The power supply lines to the AD7482 should be approximately

3 mm wide to provide low impedance paths and reduce the effects

of glitches on the power supply lines. It is vital that good decoupling

also be present. A combination of ferrites and decoupling capa-

citors should be used as shown in Figure 23. The decoupling

capacitors are to be as close to the supply pins as possible. This

is made easier by the use of multilayer boards. The signal traces

from the AD7482 pins can be run on the top layer, while the

decoupling capacitors and ferrites can be mounted on the bottom

layer where the power traces exist. The ground plane between

the top and bottom planes provides excellent shielding.

Figure 24 to Figure 28 show a sample layout of the board area

immediately surrounding the AD7482. Pin 1 is the bottom left

corner of the device. The black area in each figure indicates the

ground plane present on the middle layer Figure 24 shows the

top layer where the AD7482 is mounted with vias to the bottom

routing layer highlighted. Figure 25 shows the bottom layer

silkscreen where the decoupling components are soldered

directly beneath the device. Figure 26 shows the top and bottom

routing layers overlaid Figure 27 shows the bottom layer where

the power routing is with the same vias highlighted. Figure 28

shows the silkscreen overlaid on the solder pads for the decoupling

components, which are C1 to C6: 100 nF, C7 to C8: 470 nF, C9:

1 nF, and L1 to L4: Meggit-Sigma Chip Ferrite Beads

(BMB2A0600RS2).

Figure 24. Top Layer Routing

Figure 25. Bottom Layer Silkscreen

Figure 26. Top and Bottom Routing Layers

Figure 27. Bottom Layer Routing

Figure 28. Silkscreen and Bottom Layer Routing