AD7482

Rev. B | Page 14 of 20

Figure 18 shows the AD7482 conversion sequence when the

part is put into nap mode after each conversion.

600ns

NAP

300ns

1400ns

2µs

CONVST

BUSY

Figure 18. Nap Mode Power Dissipation

Figure 19 and Figure 20 show a typical graphical representation

of power vs. throughput for the AD7482 when in normal mode

and nap mode, respectively.

THROUGHPUT (kSPS)

60

0

3000

500

1000

1500

2000

2500

65

70

75

80

85

90

Figure 19. Normal Mode, Power vs. Throughput

THROUGHPUT (kSPS)

0

0

2000

250

750

1250

1500

1750

10

500

1000

20

30

40

50

60

70

80

90

Figure 20. Nap Mode, Power vs. Throughput

In standby mode, all the internal circuitry is powered down and the

power consumption of the AD7482 is reduced to 10

μW. The

power-up time necessary before a conversion can be initiated is

longer because more of the internal circuitry has been powered

down. In using the internal reference of the AD7482, the ADC

must be brought out of standby mode 500 ms before a conversion is

initiated. Initiating a conversion before the required power-up time

has elapsed results in incorrect conversion data. If an external

reference source is used and kept powered up while the AD7482 is

in standby mode, the power-up time required is reduced to 80 µs.

OFFSET/OVERRANGE

The AD7482 provides a ±8% overrange capability as well as a

programmable offset register. The overrange capability is achieved

by the use of a 13th bit (D12) and the CLIP input. If the CLIP input

is at logic high and the contents of the offset register are 0, then the

AD7482 operates as a normal 12-bit ADC. If the input voltage is

greater than the full-scale voltage, the data output from the ADC is

all 1s. Similarly, if the input voltage is lower than the zero-scale

voltage, the data output from the ADC is all 0s. In this case, D12

acts as an overrange indicator. It is set to 1 if the analog input

voltage is outside the nominal 0 V to 2.5 V range.

The default contents of the offset register are 0. If the offset register

contains any value other than 0, the contents of the register are

added to the SAR result at the end of conversion. This has the effect

of shifting the transfer function of the ADC as shown in Figure 21

and Figure 22. Note that with the CLIP input set to logic high, the

maximum and minimum codes that the AD7482 can output are

0xFFF and 0x000, respectively. Further details are given in Table 5

and Table 6.

Figure 21 shows the effect of writing a positive value to the

offset register. For example, if the contents of the offset register

contained the value 256, then the value of the analog input

voltage for which the ADC transitions from reading all 0s to

000...001 (the bottom reference point) is

0.5 LSB − (256 LSB) = −155.944 mV

In this example, the analog input voltage for which the ADC

reads full-scale (0xFFF) is

2.5 V − 1.5 LSB − (256 LSB) = 2.3428 V

ANALOG INPUT

0V

000...000

111...111

000...001

000...010

111...110

111...000

011...111

–OFFSET

Figure 21. Transfer Characteristic with Positive Offset

The effect of writing a negative value to the offset register is

shown in Figure 22. If a value of −128 is written to the offset

register, the bottom end reference point occurs at

0.5 LSB − (−128 LSB) = 78.43 mV

Following this, the analog input voltage needed to produce a

full-scale (0xFFF) result from the ADC is

2.5 V − 1.5 LSB − (−128 LSB) = 2.5772 V