AD7482

Rev. B | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1

IDENTIFIER

D8

D7

D6

D5

DGND

DGND

AGND

AGND

AGND

VIN

REFOUT

REFIN

REFSEL

AGND

D4

D3

D2

AD7482

TOP VIEW

(Not to Scale)

AGND

D1

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 5, 13, 46

Positive Power Supply for Analog Circuitry.

2

Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin and AGND.

3, 4, 6, 11, 12,

14, 15, 47, 48

AGND

Power Supply Ground for Analog Circuitry.

7

VIN

Analog Input. Single ended analog input channel.

8

REFOUT

Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF capacitor

must be placed between this pin and AGND.

9

REFIN

Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an external

voltage reference source, the reference voltage should be applied to this pin.

10

REFSEL

Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected from this

pin to AGND. When using an external reference source, this pin should be connected directly to AGND.

16

STBY

Standby Logic Input. When this pin is logic high, the device is placed in standby mode. See the Power Saving

section for further details.

17

NAP

Nap Logic Input. When this pin is logic high, the device is placed in a very low power mode. See the Power

Saving section for further details.

18

CS

Chip Select Logic Input. This pin is used in conjunction with RD to access the conversion result. The data bus

is brought out of three-state and the current contents of the output register driven onto the data lines

following the falling edge of both CS and RD. CS is also used in conjunction with WRITE to perform a write to

the offset register. CS can be hardwired permanently low.

19

RD

Read Logic Input. Used in conjunction with CS to access the conversion result.

20

WRITE

Write Logic Input. Used in conjunction with CS to write data to the offset register. When the desired offset

word has been placed on the data bus, the WRITE line should be pulsed high. It is the falling edge of this

pulse that latches the word into the offset register.

21

BUSY

Busy Logic Output. This pin indicates the status of the conversion process. The BUSY signal goes low after the

falling edge of CONVST and stays low for the duration of the conversion. In Parallel Mode 1, the BUSY signal

returns high when the conversion result has been latched into the output register. In Parallel Mode 2, the

BUSY signal returns high as soon as the conversion has been completed, but the conversion result does not

get latched into the output register until the falling edge of the next CONVST pulse.

22, 23

R1, R2

No Connect. These pins should be pulled to ground via 100 kΩ resistors.

24 to 28,

33 to 39

D0 to D11

Data I/O Bits. D11 is MSB. These are three-state pins that are controlled by CS, RD, and WRITE. The operating

29

Positive Power Supply for Digital Circuitry.