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TN8044AH-R0117 датащи(PDF) 56 Page - InnovASIC, Inc

номер детали TN8044AH-R0117
подробное описание детали  SDLC Communications Controller
PDF  65 Pages
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производитель  INNOVASIC [InnovASIC, Inc]
домашняя страница  http://www.innovasic.com
Logo INNOVASIC - InnovASIC, Inc

TN8044AH-R0117 датащи(HTML) 56 Page - InnovASIC, Inc

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IA8044/IA8344
Data Sheet
SDLC Communications Controller
March 30, 2010
IA211010112-04
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 56 of 65
1-888-824-4184
®
6.
Reset
A reset is accomplished by holding the RST pin high for at least two machine cycles (24
oscillator periods) while the oscillator is running. The CPU responds by generating an internal
reset, which is executed during the second cycle in which RST is high.
The internal reset sequence affects all SFRs as shown in Table 52. The internal reset sequence
does not affect the contents of internal RAM.
Table 52. Reset Values Register
Register
Reset value
PC
0000H
ACC
00000000B
B
00000000B
PSW
00000000B
SP
00000111B
DPTR
0000H
P0
–P3
11111111B
IP
XXX00000B
IE
0XX00000B
TMOD
00000000B
TCON
00000000B
TH0
00000000B
TL0
00000000B
TH1
00000000B
TL1
00000000B
SMD
00000000B
STS
00000000B
NSNR
00000000B
STAD
XXXXXXXXB
TBS
XXXXXXXXB
TBL
XXXXXXXXB
TCB
XXXXXXXXB
RBS
XXXXXXXXB
RBL
XXXXXXXXB
RFL
XXXXXXXXB
RCB
XXXXXXXXB
DMA CNT
00000000B
FIFO1
00000000B
FIFO2
00000000B
FIFO3
00000000B
SIUST
00000001B



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