AD9874ABST datasheet(36/40 Pages) AD

36 / 40 page

REV. A

AD9874

–36–

and digital driver strength should be set to their lowest pos-

sible settings to minimize the potential harmful effects of

digital induced noise while preserving a reliable data link to

the DSP. Note that the SSICRA, SSICRB, and SSIORD

registers (i.e., 0x18, 0x19, and 0x1A) provide a large degree

of flexibility for optimization of the SSI interface.

Synchronization of Multiple AD9874s

Some applications such as receiver diversity and beam steering

may require two or more AD9874s operating in parallel while

maintaining synchronization. Figure 28 shows an example of

how multiple AD9874s can be cascaded, with one device serv-

ing as the master and the other devices serving as the slaves. In

this example, all of the devices have the same SPI register con-

figuration since they share the same SPI interface to the DSP.

Since the state of each of the AD9874’s internal counters is

unknown upon initialization, synchronization of the devices is

required via a SYNCB pulse (see Figure 4) to synchronize their

digital filters and ensure precise time alignment of the data

streams.

Although all of the devices’ synthesizers are enabled, the LO

and CLK signals for the slaves(s) are derived from the masters’

synthesizers and are referenced to an external crystal oscillator.

All of the necessary external components (i.e., loop filters,

varactor, LC, and VCO) required to ensure proper closed-loop

operation of these synthesizers are included.

Note that although the VCO output of the LO synthesizer is

ac-coupled to the slave’s LO input(s), all of the CLK inputs of

the devices must be dc-coupled if the AD9874’s CLK oscillators

are enabled. This is due to the dc current required by the CLK

oscillators in each device. In essence, these negative impedance

cores are operating in parallel, increasing the effective Q of the

LC resonator circuit. Note that RBIAS should be sized such

that the sum of the oscillators’ dc bias currents maintains a

common-mode voltage of around 1.6 V.

VCO

SYNCB

DOUTA

CLKOUT

fREF

CLKP

CLKN

LOP

LON

IFIN

AD9874

MASTER

IOUTC

LOOP

FILTER

IOUTC

LOP

LON

IFIN

DOUTA

CLKOUT

SYNCB

DSP

CLKP

CLKN

IOUTL

TO DSP

FROM

DSP

LOOP

FILTER

CVAR

0.1 F

LOSC

RBIAS

COSC

TO OTHER

AD9874s

FROM

CRYSTAL

OSCILLATION

VDDC

TO OTHER

AD9874s

AD9874

SLAVE

fREF

Figure 28. Example of Synchronizing Multiple AD9874s

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